Patent US5317709A successfully refreshed from Google Patents.
US5317709A
Expired / Lapsed
US
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Microcomputer including memory controller for DRAM
Assignee: Mitsubishi Electric Corp
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Filing: 1991-03-01
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Granted: 1994-05-31
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Expires: 2011-03-01
Abstract
Abstract There is provided a microcomputer including therein a DRAM controller, the DRAM controller including a refresh controller for refreshing a DRAM and an access controller for controlling the access to the DRAM whereby the need of a DRAM controlling external circuit that suffers from severe timing adjustment is eliminated and hence the DRAM is made directly connectable to the microcomputer.
Inventors
- 👤 Masaki Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
151 words
A memory controller for a memory comprising: a refresh controller coupled to the memory for issuing a plurality of signals to control memory refresh; an access controller coupled to the memory for controlling memory access and having: (a) a memory control register including: (i) a memory area selection bit for designating a given memory area; and (ii) a memory access effective bit, wherein when said memory access effective bit is asserted, access to the given memory area designated by said memory area selection bit is enabled; (b) an access signal generator circuit, coupled to said memory control register, for generating row and column addresses and RAS and CAS signals when said effective bit is asserted; and a bus arbiter, coupled to said memory, to said access controller and to said refresh controller, for assigning a priority to one of a refresh request or an access request to said given memory area.
Claim 2
Dependent Claim
151 words
A memory controller for a memory comprising: a refresh controller coupled to the memory for issuing a plurality of signals to control memory refresh; an access controller coupled to the memory for controlling memory access and having: (a) a memory control register including: (i) a memory area selection bit for designating a given memory area; and (ii) a memory access effective bit, wherein when said memory access effective bit is asserted, access to the given memory area designated by said memory area selection bit is enabled; (b) an access signal generator circuit, coupled to said memory control register, for generating row and column addresses and RAS and CAS signals when said effective bit is asserted; and a bus arbiter, coupled to said memory, to said access controller and to said refresh controller, for assigning a priority to one of a refresh request or an access request to said given memory area.
Claim 3
Dependent Claim
76 words
The memory controller of claim 1 wherein said refresh controller further comprises: a refresh counter, coupled to an internal clock, for counting phases of said internal clock, wherein when said refresh counter is in an overflow condition, said refresh request is assigned priority by said bus arbiter over said access request; and a CAS before RAS signal generator coupled to said refresh counter and to said memory for strobing said memory to execute said refresh request.
Claim 4
Dependent Claim
48 words
The memory controller of claim 1 wherein said access controller further comprises: an address decoder, coupled to said access signal generator circuit, for decoding an address received from a central processing unit to obtain a decoded address and for outputting said decoded address to said access signal generator.
Claim 5
Dependent Claim
33 words
The memory controller of claim 1 wherein the memory comprises a 1M byte unit and wherein said memory area selection bit comprises four bits to establish memory space from 0 to 15M bytes.
Claim 6
Dependent Claim
174 words
A computer system comprising: at least one memory; a microcomputer having: (a) a CPU coupled to an internal bus; (b) a refresh controller, coupled to the internal bus and to said memory, for issuing a plurality of signals to control memory refresh; (c) an access controller coupled to the internal bus and to said memory for controlling memory access and having: (i) a memory control register including a memory area selection bit for designating a given memory area; and a memory access effective bit, wherein when said memory access effective bit is asserted, access to the given memory area designated by said memory area selection bit is enabled; (ii) an access signal generator circuit, coupled to said memory control register, for generating row and column addresses and RAS and CAS signals when said effective bit is asserted; and (d) a bus arbiter, coupled to said memory, to said access controller and to said refresh controller, for assigning a priority to one of a refresh request or an access request to said given memory area.
Claim 7
Dependent Claim
174 words
A computer system comprising: at least one memory; a microcomputer having: (a) a CPU coupled to an internal bus; (b) a refresh controller, coupled to the internal bus and to said memory, for issuing a plurality of signals to control memory refresh; (c) an access controller coupled to the internal bus and to said memory for controlling memory access and having: (i) a memory control register including a memory area selection bit for designating a given memory area; and a memory access effective bit, wherein when said memory access effective bit is asserted, access to the given memory area designated by said memory area selection bit is enabled; (ii) an access signal generator circuit, coupled to said memory control register, for generating row and column addresses and RAS and CAS signals when said effective bit is asserted; and (d) a bus arbiter, coupled to said memory, to said access controller and to said refresh controller, for assigning a priority to one of a refresh request or an access request to said given memory area.
Claim 8
Dependent Claim
76 words
The memory controller of claim 5, wherein said refresh controller further comprises: a refresh counter, coupled to an internal clock, for counting phases of said internal clock, wherein when said refresh counter is in an overflow condition, said refresh request is assigned priority by said bus arbiter over said access request; and a CAS before RAS signal generator coupled to said refresh counter and to said memory for strobing said memory to execute said refresh request.
Claim 9
Dependent Claim
48 words
The memory controller of claim 5, wherein said access controller further comprises: an address decoder, coupled to said access signal generator circuit, for decoding an address received from a central processing unit to obtain a decoded address and for outputting said decoded address to said access signal generator.
Claim 10
Dependent Claim
33 words
The memory controller of claim 5, wherein the memory comprises a 1M byte unit and wherein said memory area selection bit comprises four bits to establish memory space from 0 to 15M bytes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-30 | 1997-11-29 | 1998-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-30 | 2001-11-29 | 2002-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-30 | 2005-11-29 | 2006-05-31 | $7700.00 | Window Closed / Lapsed |