Device for effectively controlling a branch history table for an instruction prefetching system even if predictions are branch unsuccessful

Claim 1

A device for use in an instruction prefetching system for carrying out instruction prefetch in controlling branch history table means supplied with a request address signal representative of a current request address for producing a signal pair of a branch instruction address signal representative of a previously executed branch instruction address and a branch destination address corresponding to said previously executed branch instruction address, said device comprising: a prefetch control unit for outputting a detect mode signal; a detect mode register for receiving and memorizing the detect mode signal output from said prefetch control unit, said detect mode signal being indicative of, in relation to said current request address, whether said branch destination address signal should or should not be used in the instruction prefetch; detection signal producing means connected to the branch history table means and supplied with said request address signal and said branch instruction address signal for producing a detection signal indicative of whether or not said current request address coincides with said previously executed branch instruction address; first signal register means connected to said detect mode register and said detection signal producing means for indicating, when said detect mode signal indicates that said branch destination address signal should be used in the instruction prefetch, a first signal indicative of whether the instruction prefetch should or should not proceed in accordance with said branch destination address signal; and second signal register means connected to said detect mode register and said detection signal producing means for indicating, when said detect mode signal indicates that said branch destination address signal should not be used in the instruction prefetch, a second signal indicative of whether or not said current request address coincides with said historical branch instruction address; said detect mode register memorizes said detect mode signal with first and second logic levels when said branch destination address signal should and should not be used in the instruction prefetch, respectively; said detection signal producing means producing said detection signal with a predetermined one and a different one of said first and said second logic levels when said current request address is and is not coincident with said previously executed branch instruction address, respectively; said first signal register means memorizing said first signal with a preselected one and the other of said first and said second logic levels when the instruction prefetch should and should not proceed in accordance with said branch destination address signal, respectively, said preselected one of the first and the second logic levels depending on said predetermined one of the first and the second logic levels.

Claim 2

A device for use in an instruction prefetching system for carrying out instruction prefetch in controlling branch history table means supplied with a request address signal representative of a current request address for producing a signal pair of a branch instruction address signal representative of a previously executed branch instruction address and a branch destination address corresponding to said previously executed branch instruction address, said device comprising: a prefetch control unit for outputting a detect mode signal; a detect mode register for receiving and memorizing the detect mode signal output from said prefetch control unit, said detect mode signal being indicative of, in relation to said current request address, whether said branch destination address signal should or should not be used in the instruction prefetch; detection signal producing means connected to the branch history table means and supplied with said request address signal and said branch instruction address signal for producing a detection signal indicative of whether or not said current request address coincides with said previously executed branch instruction address; first signal register means connected to said detect mode register and said detection signal producing means for indicating, when said detect mode signal indicates that said branch destination address signal should be used in the instruction prefetch, a first signal indicative of whether the instruction prefetch should or should not proceed in accordance with said branch destination address signal; and second signal register means connected to said detect mode register and said detection signal producing means for indicating, when said detect mode signal indicates that said branch destination address signal should not be used in the instruction prefetch, a second signal indicative of whether or not said current request address coincides with said historical branch instruction address; said detect mode register memorizes said detect mode signal with first and second logic levels when said branch destination address signal should and should not be used in the instruction prefetch, respectively; said detection signal producing means producing said detection signal with a predetermined one and a different one of said first and said second logic levels when said current request address is and is not coincident with said previously executed branch instruction address, respectively; said first signal register means memorizing said first signal with a preselected one and the other of said first and said second logic levels when the instruction prefetch should and should not proceed in accordance with said branch destination address signal, respectively, said preselected one of the first and the second logic levels depending on said predetermined one of the first and the second logic levels.