Semiconductor memory device having voltage stress testing capability

Claim 1

A semiconductor memory device comprising: a plurality of memory cells arranged in rows and columns on a semiconductor substrate, each having one transistor and one capacitor; a plurality of word lines each connected to said memory cells in the same row; a plurality of bit lines each connected to said memory cells in the same column; a plate voltage generating circuit for generating a capacitor plate voltage during normal operation; a negative pulse generating circuit responsive to a control signal supplied thereto during voltage stress testing, for generating a pulse voltage of negative polarity; a switch circuit for supplying the pulse voltage of negative polarity output from said negative pulse generating circuit to the plate electrodes of said capacitors of all memory cells simultaneously, in place of the output of said plate voltage generating circuit; and a switch control circuit responsive to said control signal supplied thereto during voltage stress testing, for controlling said switch circuit, wherein the semiconductor memory device is formed in a chip region of a semiconductor wafer, and wherein said negative pulse generating circuit is also provided for other chip regions of the same semiconductor wafer.