Linear voltage to current converter including feedback network

Claim 2

A voltage to current converter comprising: first, second, and third field effect transistors (FETs), the sources of which are electrically connected to define a common source node; first and second voltage inputs electrically connected to the gate of said first FET and the gate of said second FET, respectively; first and second current outputs electrically connected to the drain of said first FET and the drain of said second FET, respectively; and a feedback network, electrically connected between the drain of said third FET and the common source node for maintaining constant current through said third FET.

Claim 3

The voltage to current converter of claim 1 wherein said feedback network includes a first current mirror electrically connected to the common source node.

Claim 4

The voltage to current converter of claim 2 wherein said feedback network further includes a fourth FET arranged as a common drain follower, the gate of which is electrically connected to the drain of said third FET, and the source of which is electrically connected to said first current mirror.

Claim 5

The voltage to current converter of claim 3 further comprising a second current mirror and a current source, serially connected to the drain of said third FET.

Claim 6

The voltage to current converter of claim 4 wherein said first current mirror includes two bipolar transistors and wherein said second current mirror includes a fifth FET and a sixth FET.

Claim 7

The voltage to current converter of claim 5 wherein said two bipolar transistors of said first current mirror have common base and common emitter connections.

Claim 8

The voltage to current converter of claim 5 wherein said two FETs of said second current mirror have common gate and common source connections.

Claim 9

The voltage to current converter of claim 7 further comprising a first reference voltage electrically connected to the drain of said fourth FET, the source of said fifth FET, and the source of said sixth FET.

Claim 10

The voltage to current converter of claim 6 further comprising a second reference voltage electrically connected to said current source and the emitters of said two bipolar transistors.

Claim 11

The voltage to current converter of claim 1 electrically connected in parallel to a second voltage to current converter to form an analog four quadrant multiplier.

Claim 12

A voltage to current converter comprising: first, second, and third field effect transistors (FETs), the sources of which are electrically connected to define a common source node; first and second voltage inputs electrically connected to the gate of said first FET and the gate of said second FET, respectively; first and second current outputs electrically connected to the drain of said first FET and the drain of said second FET, respectively; and a feedback network, electrically connected between the drain of said third FET and the common source node for varying the voltage between the common source node and ground in response to changes in said first and second voltage inputs in order to maintain constant current through said third FET.

Claim 13

A voltage to current converter comprising: first, second, and third field effect transistors (FETs), the sources of which are electrically connected to define a common source node; first and second voltage inputs electrically connected to the gate of said first FET and the gate of said second FET, respectively; first and second current outputs electrically connected to the drain of said first FET and the drain of said second FET, respectively; and a feedback network, electrically connected between the drain of said third FET and the common source node for varying the voltage between the common source node and ground in response to changes in said first and second voltage inputs in order to maintain constant current through said third FET.

Claim 14

The voltage to current converter of claim 11 wherein said feedback network includes a first current mirror electrically connected to the common source node.

Claim 15

The voltage to current converter of claim 12 wherein said feedback network further includes a fourth FET arranged as a common drain follower, the gate of which is electrically connected to the drain of said third FET, and the source of which is electrically connected to said first current mirror.

Claim 16

The voltage to current converter of claim 13 further comprising a second current mirror and a current source, serially connected to the drain of said third FET.

Claim 17

The voltage to current converter of claim 14 wherein said first current mirror includes two bipolar transistors and wherein said second current mirror includes a fifth FET and a sixth FET.

Claim 18

The voltage to current converter of claim 15 wherein said two bipolar transistors of said first current mirror have common base and common emitter connections.

Claim 19

The voltage to current converter of claim 15 wherein said two FETs of said second current mirror have common gate and common source connections.

Claim 20

The voltage to current converter of claim 17 further comprising a first reference voltage electrically connected to the drain of said fourth FET, the source of said fifth FET, and the source of said sixth FET.

Claim 21

The voltage to current converter of claim 16 further comprising a second reference voltage electrically connected to said current source and the emitters of said two bipolar transistors.

Claim 22

The voltage to current converter of claim 11 electrically connected in parallel to a second voltage to current converter to form an analog four quadrant multiplier.

Claim 23

The voltage to current converter of claim 11 electrically connected in parallel to a second and third voltage to current converter to form an analog four quadrant multiplier.

Claim 24

A voltage to current converter comprising: first, second, and third field effect transistors (FETs) the sources of which are electrically connected to define a common source node; first and second voltage inputs electrically connected to the gate of said first FET and the gate of said second FET, respectively; first and second current outputs electrically connected to the drain of said first FET and the drain of said second FET, respectively; a fourth FET, the gate of which is electrically connected the drain of said third FET; a first bipolar transistor, the collector of which is electrically connected to both the source of said fourth FET and the base of said first bipolar transistor; a second bipolar transistor, the collector of which is electrically connected to said common source node, the base of which is electrically connected to the base of said first bipolar transistor, and the emitter of which is electrically connected to the emitter of said first bipolar transistor; a fifth FET, the drain of which is electrically connected to the drain of said third FET; a sixth FET, the drain of which is electrically connected to both the gate of said fifth FET and the gate of said sixth FET; a current source which is electrically connected to the drain of said sixth FET; a first reference voltage which is electrically connected to the drain of said fourth FET, the source of said fifth FET, and the source of said sixth FET; and a second reference voltage electrically connected to said current source, the emitter of said first bipolar transistor, and the emitter of said second bipolar transistor.

Claim 25

A voltage to current converter comprising: first, second, and third field effect transistors (FETs) the sources of which are electrically connected to define a common source node; first and second voltage inputs electrically connected to the gate of said first FET and the gate of said second FET, respectively; first and second current outputs electrically connected to the drain of said first FET and the drain of said second FET, respectively; a fourth FET, the gate of which is electrically connected the drain of said third FET; a first bipolar transistor, the collector of which is electrically connected to both the source of said fourth FET and the base of said first bipolar transistor; a second bipolar transistor, the collector of which is electrically connected to said common source node, the base of which is electrically connected to the base of said first bipolar transistor, and the emitter of which is electrically connected to the emitter of said first bipolar transistor; a fifth FET, the drain of which is electrically connected to the drain of said third FET; a sixth FET, the drain of which is electrically connected to both the gate of said fifth FET and the gate of said sixth FET; a current source which is electrically connected to the drain of said sixth FET; a first reference voltage which is electrically connected to the drain of said fourth FET, the source of said fifth FET, and the source of said sixth FET; and a second reference voltage electrically connected to said current source, the emitter of said first bipolar transistor, and the emitter of said second bipolar transistor.

Claim 26

The voltage to current converter of claim 22 wherein said current source is a constant current source.

Claim 27

The voltage to current converter of claim 22 wherein the gate of said third FET is electrically connected to a constant voltage source.

Claim 28

The voltage to current converter of claim 22 wherein said current source is a variable current source and the gate of said third FET is electrically connected to a variable voltage source.

Claim 29

A voltage to current converter comprising: first and second field effect transistors (FETs), the sources of which are electrically connected to define a first common source node; third and fourth FETs, the sources of which are electrically connected to define a second common source node; a first voltage input electrically connected to the gate of said first FET and the gate of said third FET; a second voltage input electrically connected to the gate of said second FET and the gate of said fourth FET; first and second current outputs electrically connected to the drain of said third FET and the drain of said second FET, respectively; a first feedback network electrically connected between the drain of said first FET and said first common source node for maintaining constant current through said first FET; and a second feedback network electrically connected between the drain of said fourth FET and said second common source node for maintaining constant current through said fourth FET.

Claim 30

A voltage to current converter comprising: first and second field effect transistors (FETs), the sources of which are electrically connected to define a first common source node; third and fourth FETs, the sources of which are electrically connected to define a second common source node; a first voltage input electrically connected to the gate of said first FET and the gate of said third FET; a second voltage input electrically connected to the gate of said second FET and the gate of said fourth FET; first and second current outputs electrically connected to the drain of said third FET and the drain of said second FET, respectively; a first feedback network electrically connected between the drain of said first FET and said first common source node for maintaining constant current through said first FET; and a second feedback network electrically connected between the drain of said fourth FET and said second common source node for maintaining constant current through said fourth FET.

Claim 31

The voltage to current converter of claim 26 wherein said first and second feedback networks, vary the voltage between their respective common source nodes and ground in response to changes in said first and second voltage inputs in order to maintain constant current through said first and said fourth FETs, respectively.

Claim 32

The voltage to current converter of claim 27 wherein said first feedback network includes a first current mirror electrically connected to said first common source node and said second feedback network includes a second current mirror electrically connected to said second common source node.

Claim 33

The voltage to current converter of claim 28 wherein said first and second feedback networks further include a fifth and a sixth FET respectively arranged as common drain followers, the gates of which are electrically connected to the drains of said first and fourth FETs, respectively, and the sources of which are electrically connected to said first and second current mirrors, respectively.

Claim 34

The voltage to current converter of claim 29 further comprising a third current mirror and a current source, serially connected between the drains of said first and fourth FETs and a reference voltage.

Claim 35

The voltage to current converter of claim 28 wherein said first current mirror includes two bipolar transistors, said second current mirror includes two bipolar transistors, and wherein said third current mirror includes a seventh FET, an eighth FET, and a ninth FET.

Claim 36

A voltage to current converter comprising: first and second field effect transistors (FETs), the sources of which are electrically connected to define a first common source node; third and fourth FETs, the sources of which are electrically connected to define a second common source node; a first voltage input electrically connected to the gate of said first FET and the gate of said third FET; a second voltage input electrically connected to the gate of said second FET and the gate of said fourth FET; first and second current outputs electrically connected to the drain of said third FET and the drain of said second FET, respectively; a fifth FET arranged as a common drain follower, the gate of which is electrically connected to the drain of said first FET; a first reference voltage which is electrically connected to the drain of said fifth FET; a sixth FET arranged as a common drain follower, the gate of which is electrically connected to the drain of said fourth FET, and the drain of which is electrically connected to said first reference voltage; a seventh FET the source of which is electrically connected to said first reference voltage, and the drain of which is electrically connected to the drain of said first FET; a current source which is electrically connected to the gate of said seventh FET; a second reference voltage which is electrically connected to said current source; an eighth FET the source of which is electrically connected to said first reference voltage, the drain of which is electrically connected to said current source, and the gate of which is electrically connected to said current source; a ninth FET the source of which is electrically connected to said first reference voltage, the drain of which is electrically connected to the drain of said fourth FET, and the gate of which is electrically connected to said current source; a first bipolar transistor, the collector of which is electrically connected to both the source of said fifth FET and the base of said first bipolar transistor, and the emitter of which is electrically connected said second reference voltage; a second bipolar transistor, the collector of which is electrically connected to said first common source node, the base of which is electrically connected to the base of said first bipolar transistor, and the emitter of which is electrically connected to said second reference voltage; a third bipolar transistor, the collector of which is electrically connected to both the source of said sixth FET and the base of said third bipolar transistor, and the emitter of which is electrically connected said second reference voltage; and a fourth bipolar transistor, the collector of which is electrically connected to said second common source node, the base of which is electrically connected to the base of said third bipolar transistor, and the emitter of which is electrically connected to said second reference voltage.

Claim 37

A voltage to current converter comprising: first and second field effect transistors (FETs), the sources of which are electrically connected to define a first common source node; third and fourth FETs, the sources of which are electrically connected to define a second common source node; a first voltage input electrically connected to the gate of said first FET and the gate of said third FET; a second voltage input electrically connected to the gate of said second FET and the gate of said fourth FET; first and second current outputs electrically connected to the drain of said third FET and the drain of said second FET, respectively; a fifth FET arranged as a common drain follower, the gate of which is electrically connected to the drain of said first FET; a first reference voltage which is electrically connected to the drain of said fifth FET; a sixth FET arranged as a common drain follower, the gate of which is electrically connected to the drain of said fourth FET, and the drain of which is electrically connected to said first reference voltage; a seventh FET the source of which is electrically connected to said first reference voltage, and the drain of which is electrically connected to the drain of said first FET; a current source which is electrically connected to the gate of said seventh FET; a second reference voltage which is electrically connected to said current source; an eighth FET the source of which is electrically connected to said first reference voltage, the drain of which is electrically connected to said current source, and the gate of which is electrically connected to said current source; a ninth FET the source of which is electrically connected to said first reference voltage, the drain of which is electrically connected to the drain of said fourth FET, and the gate of which is electrically connected to said current source; a first bipolar transistor, the collector of which is electrically connected to both the source of said fifth FET and the base of said first bipolar transistor, and the emitter of which is electrically connected said second reference voltage; a second bipolar transistor, the collector of which is electrically connected to said first common source node, the base of which is electrically connected to the base of said first bipolar transistor, and the emitter of which is electrically connected to said second reference voltage; a third bipolar transistor, the collector of which is electrically connected to both the source of said sixth FET and the base of said third bipolar transistor, and the emitter of which is electrically connected said second reference voltage; and a fourth bipolar transistor, the collector of which is electrically connected to said second common source node, the base of which is electrically connected to the base of said third bipolar transistor, and the emitter of which is electrically connected to said second reference voltage.