Compensated digital delay circuit

Claim 2

A compensated digital delay circuit having a design format suited for integrated circuitry utilizing complementary MOS technology comprising: an input for signals-to-be-delayed; a delay line with a plurality of time delay cells connected to said input, each of said time delay cells selectively interconnectable for forming one or more delay configurations, said delay line having a first output therefrom; first circuit means for generating a variable current from a control voltage, said first circuit means connected to said time delay cells; internal compensation means for compensating temperature and power supply variations, said internal compensation means connected to said first circuit means to adjust the time delay of the delay cells, said internal compensation means, in turn, comprising: ring oscillator means for temperature and power supply compensation, said oscillator means having time delay cells selected for interchangeability with those of said delay line, said first output of said delay line connected to the ring oscillator, said ring oscillator having a second output therefrom; second circuit means for generating a variable current from a reference voltage, said second circuit means connected to said ring oscillator; and, control circuit means for generating a variable voltage signals for connection to said first circuit means to adjust the current to the time delay cells, said control circuit means connected to said second output of said ring oscillator; whereby a precision delay line is formed from complementary MOS technology employing an oscillator means to compensate for temperature and power supply variations and without using a reference frequency for timing.

Claim 3

A compensated digital delay circuit as described in claim 1 wherein each of said time delay cells means further comprises: a plurality of selectable capacitive elements arrayed therewithin in a weighted manner; and, a plurality of selectable current sources arrayed therewithin in a weighted manner.

Claim 4

A compensated digital delay circuit as described in claim 2 further comprising: first memory means for selecting one or more of said plurality of capacitive elements, said memory means being programmable to function cooperatively with said delay cell and interconnected therewith to switch differently rated capacitive elements into and out of said circuit; second memory means for selecting one or more of said plurality of current sources, said memory means being programmable to function cooperatively with said time delay and interconnected therewith to switch differently rated current sources into and out of said circuit; and, wherein: said ring oscillator means has identically selected capacitive elements and current sources as the corresponding delay line.

Claim 5

A compensated digital delay circuit as described in claim 3 wherein said ring oscillator means for temperature and power supply compensation further includes identically selectable capacitive elements and current sources as the corresponding delay lines.

Claim 6

A compensated digital delay circuit as described in claim 4 wherein said control circuit means includes a delay-to-voltage circuit means for converting the delay line time of said oscillator to a voltage control signal.

Claim 7

A compensated digital delay circuit as described in claim 5 wherein said delay-to-voltage circuit means further comprises: a delay-to-pulse-width converter and a pulse-width-to-voltage converter; and, a pulse-width distortion compensation means for compensating the delay line for switching nonlinearities, said pulse-width compensation means proportionally increasing and decreasing one of said delay cell complementary current source magnitude so as to thereby cancel transfer function deviations.

Claim 8

A compensated digital delay circuit as described in claim 2 wherein said capacitive elements are weighted in a binary series format with each successive capacitive element in the series having twice the capacitance of the preceeding one.

Claim 9

A compensated digital delay circuit as described in claim 7 wherein said selection of said capacitive elements enables the selection of a time delay subrange that encompasses deviations arising from process variations.

Claim 10

A compensated digital delay circuit as described in claim 2 wherein said current sources are weighted in a binary series format with each successive current source in the series having twice the rating of the preceeding one.

Claim 11

A compensated digital delay circuit as described in claim 9 wherein said selection of said current sources enables the selection of a precise time delay that, with the capacitive element selection, is in the sub-nanosecond range.

Claim 12

A compensated digital delay circuit having a design format suited for integrated circuitry with components deposited thereon by complementary MOS technology comprising: a first input for signals-to-be-delayed; a delay line connected to said first input with a plurality of time delay cells selectively interconnectable, for forming one or more delay lines, each of said time delay cell having a first plurality of controllably selectable circuit components, including capacitive elements and current sources, said delay line having a first memory input means for programmably selecting circuit components; first circuit means for generating a variable current from a control voltage, said first circuit means connected to said time delay cells; ring oscillator means for temperature and power supply compensation, said oscillator means formed from a second plurality of time delay cells selected for interchangeability with said plurality of time delay cells, each oscillator means having identically selected capacitive elements and current sources as the corresponding delay line, said ring oscillator having a second memory input means for programmably selecting circuit components; a non-volatile memory for selecting one or more said components within said integrated circuitry, said memory operative to switch said components into and out of the programmable compensated digital delay circuit, said non-volatile memory connected to said first memory input means of said delay line and to said second memory input means of said ring oscillator; a second input for receiving said reference voltage, said second input connected to said ring oscillator; and, error voltage circuit means for generating an error voltage signal, said error voltage circuit means connected to said first circuit means for adjustment of the control voltage to the programmable compensated digital delay circuit; whereby a precision delay line is formed from complementary MOS technology without using a reference frequency for timing.

Claim 13

A compensated digital delay circuit having a design format suited for integrated circuitry with components deposited thereon by complementary MOS technology comprising: a first input for signals-to-be-delayed; a delay line connected to said first input with a plurality of time delay cells selectively interconnectable, for forming one or more delay lines, each of said time delay cell having a first plurality of controllably selectable circuit components, including capacitive elements and current sources, said delay line having a first memory input means for programmably selecting circuit components; first circuit means for generating a variable current from a control voltage, said first circuit means connected to said time delay cells; ring oscillator means for temperature and power supply compensation, said oscillator means formed from a second plurality of time delay cells selected for interchangeability with said plurality of time delay cells, each oscillator means having identically selected capacitive elements and current sources as the corresponding delay line, said ring oscillator having a second memory input means for programmably selecting circuit components; a non-volatile memory for selecting one or more said components within said integrated circuitry, said memory operative to switch said components into and out of the programmable compensated digital delay circuit, said non-volatile memory connected to said first memory input means of said delay line and to said second memory input means of said ring oscillator; a second input for receiving said reference voltage, said second input connected to said ring oscillator; and, error voltage circuit means for generating an error voltage signal, said error voltage circuit means connected to said first circuit means for adjustment of the control voltage to the programmable compensated digital delay circuit; whereby a precision delay line is formed from complementary MOS technology without using a reference frequency for timing.

Claim 14

A compensated digital delay circuit as described in claim 11 wherein said first plurality of time delay cells further comprises: a plurality of controllable capacitive elements arrayed therewithin in a weighted manner; and, a plurality of controllable current sources arrayed therewithin in a weighted manner.

Claim 15

A compensated digital delay circuit as described in claim 11 wherein said non-volatile memory further comprises: first memory means for selecting one or more of said plurality of capacitive elements, said memory means being programmable to function cooperatively with said delay cell and to switch differently rated capacitive elements into and out of said circuit; second memory means for selecting one or more of said plurality of current sources, said memory means being programmable to function cooperatively with said delay cell and to switch differently rated current sources into and out of said circuit.

Claim 16

A programmable compensated digital delay circuit as described in claim 19 wherein said delay-to-voltage circuit means further comprises a delay-to-pulse-width converter and pulse-width-to-voltage converter.

Claim 17

A compensated digital delay circuit as described in claim 14 wherein said capacitive elements are weighted in a binary series format with each successive capacitive element in the series having twice the capacitance of the preceeding one.

Claim 18

A digital delay circuit as described in claim 15 wherein said selection of said capacitive elements enables the selection of a time delay subrange that encompasses deviations arising from process variations.

Claim 19

A compensated digital delay circuit as described in claim 11 further includes: a pulse-width distortion compensation means for compensating the delay line for switching nonlinearities, said pulse-width compensation means proportionally increasing and decreasing an output of said controllably selectable current source of said delay cell to thereby cancel transfer function deviations.

Claim 20

A compensated digital delay circuit as described in claim 11 further comprising: second circuit means for generating a variable current current from a reference voltage, said second circuit means connected to said ring oscillator; and, control circuit means for generating a variable voltage signal for connection to said first circuit means to adjust the current to the time delay cells, said control circuit means connected to said second output of said ring oscillator.

Claim 21

A compensated digital delay circuit as described in claim 18 wherein said control circuit means further comprises: a delay-to-voltage circuit means for converting the delay line time of said oscillator to a voltage control signal.