Semiconductor integrated circuit and associated test method

Claim 2

A semiconductor integrated circuit comprising: a sequential circuit consisting of a plurality of flip-flops which latch and keep data supplied to an input terminal at a prescribed timing and which perform prescribed sequential treatments of the input data; a combinational circuit which is implemented at the input terminals of said sequential circuit and which performs a prescribed combinational treatment or treatments of the input data to said sequential circuit; data-through means operated by an external control signal designed to transfer the data supplied to the input terminal direct to an output terminal of a prescribed flip-flop of said plurality of flip-flops of said sequential circuit, wherein said flip-flops comprise a first transfer gate designed to transfer and control on and off input data in accordance with a clock signal supplied thereto, a first inverter designed to reverse the polarity of the input data signal received as the output of the first transfer gate to be transferred to the output terminal, a second inverter designed to reverse the polarity of the input data signal received as the output of the first inverter, a second transfer gate designed to transfer and control the output data of said second inverter turned on and off by the clock signal of opposite polarity to said first transfer gate, and wherein data-through means comprises a third transfer gate connected in parallel to said first transfer gate and turned on and off by said external control signal, and a fourth transfer gate connected in series to said second transfer gate and turned on and off in opposite polarity of said third transfer gate by said external control signal.

Claim 3

A semiconductor integrated circuit comprising: a sequential circuit consisting of a plurality of flip-flops which latch and keep data supplied to an output terminal at a prescribed timing and which perform prescribed sequential treatments of the input data; a combinational circuit which is implemented at the output terminals of said sequential circuit and which performs a prescribed combinational treatment or treatments of the output data from said sequential circuit; data-through means operated by an external control signal designed to transfer the data supplied to the input terminal direct to an output terminal of a prescribed flip-flop of said flip-flops of said sequential circuit, wherein said flip-flops comprise a first transfer gate designed to transfer and control on and off input data in accordance with a clock signal supplied thereto, a first inverter designed to reverse the polarity of the input data signal received as the output of the first transfer gate to be transferred to the output terminal, a second inverter designed to reverse the polarity of the input data signal received as the output of the first inverter, a second transfer gate designed to transfer and control the output data of said second inverter turned on and off by the clock signal of the opposite polarity to said first transfer gate, and wherein said data-through means comprises a third transfer gate connected in parallel to said first transfer gate and turned on and off by said external control signal, and a fourth transfer gate connected in series to said second transfer gate and turned on and off in opposite polarity of said third transfer gate by said external control signal.

Claim 4

A semiconductor integrated circuit comprising: a sequential circuit consisting of a plurality of flip-flops which latch and keep data supplied to an output terminal at a prescribed timing and which perform prescribed sequential treatments of the input data; a combinational circuit which is implemented at the output terminals of said sequential circuit and which performs a prescribed combinational treatment or treatments of the output data from said sequential circuit; data-through means operated by an external control signal designed to transfer the data supplied to the input terminal direct to an output terminal of a prescribed flip-flop of said flip-flops of said sequential circuit, wherein said flip-flops comprise a first transfer gate designed to transfer and control on and off input data in accordance with a clock signal supplied thereto, a first inverter designed to reverse the polarity of the input data signal received as the output of the first transfer gate to be transferred to the output terminal, a second inverter designed to reverse the polarity of the input data signal received as the output of the first inverter, a second transfer gate designed to transfer and control the output data of said second inverter turned on and off by the clock signal of the opposite polarity to said first transfer gate, and wherein said data-through means comprises a third transfer gate connected in parallel to said first transfer gate and turned on and off by said external control signal, and a fourth transfer gate connected in series to said second transfer gate and turned on and off in opposite polarity of said third transfer gate by said external control signal.

Claim 5

A test method for the semiconductor integrated circuit including: a sequential circuit consisting of a plurality of flip-flops which latch and keep data supplied to an input terminal at a prescribed timing and which perform prescribed sequential treatments of the input data; a combinational circuit which is implemented at the input terminals of said sequential circuit and which performs a prescribed combinational treatment or treatments of the input data to said sequential circuit; data-through means operated by an external control signal designed to transfer the data supplied to the input terminal direct to an output terminal of a prescribed flip-flop of said plurality of flip-flops of said sequential circuit, the flip-flops including a first transfer gate designed to transfer and control on and off input data in accordance with a clock signal, a first inverter designed to reverse the polarity of the input data signal received as the output of the first transfer gate to be transferred to the output terminal, a second inverter designed to reverse the polarity of the input data signal received as the output of the first inverter, a second transfer gate designed to transfer and control the output data of said second inverter turned on and off by the clock signal of opposite polarity to said first transfer gate, and data-through means including a third transfer gate connected in parallel to said first transfer gate and turned on and off by said external control signal, and a fourth transfer gate connected in series to said second transfer gate and turned on and off in opposite polarity of said third transfer gate by said external control signal, the method comprising the steps of: operating a prescribed flip-flop out of said plurality of flip-flops constituting the sequential circuit in the data-through mode by applying said external control signal in order to make the entire semiconductor integrated circuit a signal combinational circuit in which the input data is transferred direct to the output terminal, thereby making it possible to test the semiconductor integrated circuit using ordinary data as the input signal.

Claim 6

A test method for the semiconductor integrated circuit including: a sequential circuit consisting of a plurality of flip-flops which latch and keep data supplied to an input terminal at a prescribed timing and which perform prescribed sequential treatments of the input data; a combinational circuit which is implemented at the input terminals of said sequential circuit and which performs a prescribed combinational treatment or treatments of the input data to said sequential circuit; data-through means operated by an external control signal designed to transfer the data supplied to the input terminal direct to an output terminal of a prescribed flip-flop of said plurality of flip-flops of said sequential circuit, the flip-flops including a first transfer gate designed to transfer and control on and off input data in accordance with a clock signal, a first inverter designed to reverse the polarity of the input data signal received as the output of the first transfer gate to be transferred to the output terminal, a second inverter designed to reverse the polarity of the input data signal received as the output of the first inverter, a second transfer gate designed to transfer and control the output data of said second inverter turned on and off by the clock signal of opposite polarity to said first transfer gate, and data-through means including a third transfer gate connected in parallel to said first transfer gate and turned on and off by said external control signal, and a fourth transfer gate connected in series to said second transfer gate and turned on and off in opposite polarity of said third transfer gate by said external control signal, the method comprising the steps of: operating a prescribed flip-flop out of said plurality of flip-flops constituting the sequential circuit in the data-through mode by applying said external control signal in order to make the entire semiconductor integrated circuit a signal combinational circuit in which the input data is transferred direct to the output terminal, thereby making it possible to test the semiconductor integrated circuit using ordinary data as the input signal.

Claim 7

A test method for the semiconductor integrated circuit including a sequential circuit consisting of a plurality of flip-flops which latch and keep data supplied to an input terminal at a prescribed timing and which perform prescribed sequential treatments of the input data; a combinational circuit which is implemented at the output temrainls of said sequential circuit and which performs a prescribed combinational treatment or treatments of the output data from said sequential circuit; and data-through means operated by an external control signal designed to transfer the data supplied to the input terminal direct to an output terminal of a prescribed flip-flop of said plurality of flip-flops of said sequential circuit, the flip-flops including a first transfer gate designed to transfer and control on and off input data in accordance with a clock signal, a first inverter designed to reverse the polarity of the input data signal received as the output of the first transfer gate to be transferred to the output terminal, a second inverter designed to reverse the polarity of the input data signal received as the output of the first inverter, a second transfer gate designed to transfer and control the output data of said second inverter turned on and off by the clock signal of opposite polarity to said first transfer gate, and data-through means including a third transfer gate connected in parallel to said first transfer gate and turned on and off by said external control signal, and a fourth transfer gate connected in series to said second transfer gate and turned on and off in opposite polarity of said third transfer gate by said external control signal, the method comprising the steps of: operating a prescribed flip-flop out of said plurality of flip-flops constituting the sequential circuit in the data-through mode by applying said external control signal in order to make the entire semiconductor integrated circuit a signal combinational circuit in which the input data is transferred direct to the output terminal, thereby making it possible to test the semiconductor integrated circuit using ordinary data as the input signal.

Claim 8

A test method for the semiconductor integrated circuit including a sequential circuit consisting of a plurality of flip-flops which latch and keep data supplied to an input terminal at a prescribed timing and which perform prescribed sequential treatments of the input data; a combinational circuit which is implemented at the output temrainls of said sequential circuit and which performs a prescribed combinational treatment or treatments of the output data from said sequential circuit; and data-through means operated by an external control signal designed to transfer the data supplied to the input terminal direct to an output terminal of a prescribed flip-flop of said plurality of flip-flops of said sequential circuit, the flip-flops including a first transfer gate designed to transfer and control on and off input data in accordance with a clock signal, a first inverter designed to reverse the polarity of the input data signal received as the output of the first transfer gate to be transferred to the output terminal, a second inverter designed to reverse the polarity of the input data signal received as the output of the first inverter, a second transfer gate designed to transfer and control the output data of said second inverter turned on and off by the clock signal of opposite polarity to said first transfer gate, and data-through means including a third transfer gate connected in parallel to said first transfer gate and turned on and off by said external control signal, and a fourth transfer gate connected in series to said second transfer gate and turned on and off in opposite polarity of said third transfer gate by said external control signal, the method comprising the steps of: operating a prescribed flip-flop out of said plurality of flip-flops constituting the sequential circuit in the data-through mode by applying said external control signal in order to make the entire semiconductor integrated circuit a signal combinational circuit in which the input data is transferred direct to the output terminal, thereby making it possible to test the semiconductor integrated circuit using ordinary data as the input signal.