US5317178A
Expired / Lapsed
US
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Offset dual gate thin film field effect transistor
Assignee: Industrial Technology Research Institute
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Filing: 1993-07-22
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Granted: 1994-05-31
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Expires: 2013-07-22
Abstract
Abstract A field effect transistor having a thin polycrystalline silicon layer as a channel region, a lower gate electrode beneath the silicon layer, and upper gate electrode with an offset above the silicon layer, and a gate dielectric layer between the lower gate electrode and the silicon layer, and a gate dielectric layer between the upper gate electrode and the silicon layer.
Inventors
- 👤 Neng-Wei Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10B; H10B10/00; H10B10/12; H10B10/125; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10D30/674; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
123 words
An offset dual gate thin film field effect transistor comprising: an insulating substrate; a narrow stripe of conductive material on said substrate to serve as a lower gate electrode; a first thin gate dielectric layer over said lower gate electrode; a layer of polycrystalline silicon over said lower gate electrode and extending beyond the edges thereof; a second gate dielectric layer over said layer of polycrystalline silicon; a upper offset gate electrode located over said lower gate electrode with a portion thereof providing an offset in the range of 0.2 to 0.6 micrometers extending beyond one edge of said lower gate electrode; source and drain regions in said layer of polycrystalline silicon layer located beyond opposite edges of said upper offset gate electrode.
Claim 2
Dependent Claim
123 words
An offset dual gate thin film field effect transistor comprising: an insulating substrate; a narrow stripe of conductive material on said substrate to serve as a lower gate electrode; a first thin gate dielectric layer over said lower gate electrode; a layer of polycrystalline silicon over said lower gate electrode and extending beyond the edges thereof; a second gate dielectric layer over said layer of polycrystalline silicon; a upper offset gate electrode located over said lower gate electrode with a portion thereof providing an offset in the range of 0.2 to 0.6 micrometers extending beyond one edge of said lower gate electrode; source and drain regions in said layer of polycrystalline silicon layer located beyond opposite edges of said upper offset gate electrode.
Claim 3
Dependent Claim
22 words
The thin film transistor of claim 1 wherein said narrow stripe has a width in the range of 0.4 to 1.8 micrometers.
Claim 4
Dependent Claim
30 words
The thin film transistor of claim 2 wherein the impurity in said source and drain regions is BF 2 , in a concentration in the range of 5E18 to 5E20.
Claim 5
Dependent Claim
24 words
The thin film transistor of claim 3 wherein the thickness of said polycrystalline silicon layer is in the range of 50 to 1000 Angstroms.
Claim 6
Dependent Claim
33 words
The thin film transistor of claim 1 wherein the ratio of the thicknesses of the second gate dielectric layer to the first gate dielectric layer is in the range of 2 to 10.
Claim 7
Dependent Claim
37 words
The offset dual gate thin film field effect transistor of claim 1, wherein a plurality of said transistors are embodied as integral elements of a static random access memory device having a plurality of CMOS flip-flop circuits.
Claim 8
Dependent Claim
35 words
The transistor of claim 6, wherein each of said CMOS circuits embodies a first thin film FET, and an associated second thin film FET having a channel of a conductivity opposite to said first FET.
Claim 9
Dependent Claim
37 words
The transistor of claim 7, wherein the offset of the upper gate electrode beyond the edge of said lower gate electrode of said first and said second transistor, is in the range of 0.2 to 0.6 micrometers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-30 | 1997-11-29 | 1998-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-30 | 2001-11-29 | 2002-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-30 | 2005-11-29 | 2006-05-31 | $7700.00 | Window Closed / Lapsed |