Patent US5316959A successfully refreshed from Google Patents.
US5316959A
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Trenched DMOS transistor fabrication using six masks
Assignee: Vishay Siliconix Inc
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Filing: 1992-08-12
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Granted: 1994-05-31
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Expires: 2012-08-12
Abstract
Abstract A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.
Inventors
- 👤 Sze-Hon Kwan
- 👤 Fwu-Iuan Hshieh
- 👤 Mike F. Chang
- 👤 Yueh-Se Ho
- 👤 King Owyang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:58
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/665; H10D30/668; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/106
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
233 words
A method for forming a field effect transistor comprising: providing a semiconductor substrate having a principal surface and being of a first conductivity type; forming a patterned mask layer on the principal surface; doping semiconductor regions of a second conductivity type in the portions of the substrate exposed by the mask layer, thereby forming deep body regions of the transistor; growing an oxide layer on the portions of the principal surface exposed by the mask layer; forming a plurality of trenches in the substrate; forming a layer of conductive material in the trenches and over at least a part of the oxide layer, the portion of the conductive material layer in the trenches being a gate of the transistor; forming doped first regions of the second conductivity type in the substrate extending from the portions of the principal surface not covered by the oxide layer or the layer of conductive material into the substrate; forming doped second regions of the first conductivity type extending from the unmasked portions of the principal surface into the substrate, the first and second doped regions respectively being body and source regions of the transistor; forming a patterned insulating layer overlying the principal surface and the conductive material layer; and forming a patterned interconnect layer overlying the principal surface and over the patterned insulating layer and contacting the deep body, body, and source regions, and the gate electrode.
Claim 2
Independent Claim
233 words
A method for forming a field effect transistor comprising: providing a semiconductor substrate having a principal surface and being of a first conductivity type; forming a patterned mask layer on the principal surface; doping semiconductor regions of a second conductivity type in the portions of the substrate exposed by the mask layer, thereby forming deep body regions of the transistor; growing an oxide layer on the portions of the principal surface exposed by the mask layer; forming a plurality of trenches in the substrate; forming a layer of conductive material in the trenches and over at least a part of the oxide layer, the portion of the conductive material layer in the trenches being a gate of the transistor; forming doped first regions of the second conductivity type in the substrate extending from the portions of the principal surface not covered by the oxide layer or the layer of conductive material into the substrate; forming doped second regions of the first conductivity type extending from the unmasked portions of the principal surface into the substrate, the first and second doped regions respectively being body and source regions of the transistor; forming a patterned insulating layer overlying the principal surface and the conductive material layer; and forming a patterned interconnect layer overlying the principal surface and over the patterned insulating layer and contacting the deep body, body, and source regions, and the gate electrode.
Claim 3
Dependent Claim
38 words
The method of claim 1, wherein the step of growing an oxide layer comprises locally oxidizing the exposed portions of the principal surface to form a layer in the range of about 5,000 to about 8,000 Å thick.
Claim 4
Dependent Claim
60 words
The method of claim 1, wherein the step of forming a plurality of trenches comprises: anisotropically etching a plurality of U-shaped trenches; smoothing the trench walls and rounding the trench corners by an isotropic plasma dry etch; growing a layer of sacrificial oxide on the sidewalls of the trenches; and removing at least part of the layer of sacrificial oxide.
Claim 5
Dependent Claim
24 words
The method of claim 3, wherein the step of forming the doped first regions is after the step of forming the plurality of trenches.
Claim 6
Dependent Claim
22 words
The method of claim 4, wherein the depth of the trenches is in the range of about 1.5 to about 3 microns.
Claim 7
Dependent Claim
99 words
The method of claim 1, wherein the step of forming a layer of conductive material comprises: depositing a layer of material in the trenches and overlying the principal surface; etching away a portion of the deposited layer; doping remaining portions of the deposited layer; forming a patterned mask layer over the doped deposited layer portions; and etching away those portions of the doped deposited layer exposed by the patterned mask layer, wherein the trenches are filled with the doped deposited layer, and the doped deposited layer is over the oxide layer only in a termination region of the transistor.
Claim 8
Dependent Claim
81 words
The method of claim 6, wherein the step of forming a patterned interconnect layer comprises: depositing a layer of metal overlying the principal surface and the patterned insulating layer; forming a patterned mask layer over the layer of metal; etching away those portions of the metal layer exposed by the patterned mask layer, and further etching away in the same step that portion of the doped deposited layer in the termination region that is not overlain by the patterned insulating layer.
Claim 9
Independent Claim
134 words
A method for forming a field effect transistor comprising the steps of: providing a semiconductor substrate having a principal surface and being of a first conductivity type; forming a patterned mask layer on the principal surface; forming a doped deep body region of a second conductivity type of the transistor in a portion of the substrate underlying the portions of the principal surface exposed by the patterned mask layer; locally growing oxide on the principal surface at those portions of the principal surface exposed by the patterned mask layer; removing the patterned mask layer, thereby exposing additional portions of the principal surface; and forming in those portions of the substrate underlying the exposed additional portions of the principal surface a doped body region, a doped source region, and a gate region of the transistor.
Claim 10
Independent Claim
134 words
A method for forming a field effect transistor comprising the steps of: providing a semiconductor substrate having a principal surface and being of a first conductivity type; forming a patterned mask layer on the principal surface; forming a doped deep body region of a second conductivity type of the transistor in a portion of the substrate underlying the portions of the principal surface exposed by the patterned mask layer; locally growing oxide on the principal surface at those portions of the principal surface exposed by the patterned mask layer; removing the patterned mask layer, thereby exposing additional portions of the principal surface; and forming in those portions of the substrate underlying the exposed additional portions of the principal surface a doped body region, a doped source region, and a gate region of the transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-30 | 1997-11-29 | 1998-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-30 | 2001-11-29 | 2002-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-30 | 2005-11-29 | 2006-05-31 | $7700.00 | Window Closed / Lapsed |