US5315540A
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US
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Method and hardware for dividing binary signal by non-binary integer number
Assignee: International Business Machines Corp
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Filing: 1992-08-18
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Granted: 1994-05-24
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Expires: 2012-08-18
Abstract
Abstract A binary signal hardware divider and method are described for a high performance computer graphics system. Each bit of an input binary signal to be divided by an integer number of a non-binary power is associated with a predetermined binary weight comprising the traditional binary weight for the bit divided by the integer number. The associated binary weights for each active bit are then summed to arrive at a resultant binary signal equal to the input binary signal divided by the integer number. A wire shifting technique for aligning selected ones of the binary weights without creation of any delay is also presented. Fast hardware divide within today's typical clock cycle is attained.
Inventors
- 👤 William F. Lawless
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:17
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393; G06F2207/00; G06F2207/535; G06F2207/5354
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
167 words
A hardware divider for a raster engine of a graphics display system, said raster engine having a given binary signal of a plurality of bits, said hardware divider for dividing said given binary signal by a predetermined integer number of a non-binary power, each of said plurality of bits having a binary power of known weight, said hardware divider comprising: means for converting each `1` bit of said given binary signal into a binary weight signal, each binary weight signal comprising a binary representation of the binary power of known weight for said `1` bit divided by said integer number, and each binary weight signal having an integer portion and a remainder portion; and means for summing each of said binary weight signals corresponding to said `1` bit of said given binary signal to derive a resultant binary signal having both an integer portion and a remainder portion, said resultant binary signal being a binary representation of said given binary signal divided by said predetermined integer number.
Claim 2
Dependent Claim
167 words
A hardware divider for a raster engine of a graphics display system, said raster engine having a given binary signal of a plurality of bits, said hardware divider for dividing said given binary signal by a predetermined integer number of a non-binary power, each of said plurality of bits having a binary power of known weight, said hardware divider comprising: means for converting each `1` bit of said given binary signal into a binary weight signal, each binary weight signal comprising a binary representation of the binary power of known weight for said `1` bit divided by said integer number, and each binary weight signal having an integer portion and a remainder portion; and means for summing each of said binary weight signals corresponding to said `1` bit of said given binary signal to derive a resultant binary signal having both an integer portion and a remainder portion, said resultant binary signal being a binary representation of said given binary signal divided by said predetermined integer number.
Claim 3
Dependent Claim
16 words
The hardware divider of claim 1, wherein said summing means includes multiple, two input combinatorial adders.
Claim 4
Dependent Claim
15 words
The hardware divider of claim 1, wherein said predetermined integer number comprises the number 5.
Claim 5
Dependent Claim
57 words
The hardware divider of claim 3, wherein said summing means separately sums said integer portions of said binary weight signals and said remainder portions of said binary weight signals in modulo 5and wherein said summing means includes means for carrying over any integer number resulting from said summing of remainder portions to said summing of integer portions.
Claim 6
Dependent Claim
65 words
The hardware divider of claim 1, wherein associated with said raster engine is a frame buffer having multiple modules, and wherein said resultant binary signal comprises an address location, said remainder portion of said resultant binary signal identifying a specific one of said multiple frame buffer modules, said integer portion of said resultant binary signal identifying a column address within said identified frame buffer module.
Claim 7
Dependent Claim
27 words
The hardware divider of claim 1, wherein said summing means includes means for obtaining said resultant binary signal within a single clock cycle of the raster engine.
Claim 8
Dependent Claim
42 words
The hardware divider of claim 1, wherein said combinatorial logic receives preselected pairs of said bits comprising said given binary signal, said bits of each preselected pair having mutually exclusive binary weight signals when said paired bits both comprise a `1` bit.
Claim 9
Dependent Claim
124 words
A hardware circuit for adding predetermined binary quotients associated with preselected digits of a given binary signal, each digit of said binary signal having a predetermined binary quotient associated therewith when having an active `1` value, said hardware circuit comprising: a wire shifting circuit wherein binary quotients associated with preselected pairs of said bits comprising said given binary signal are combined by wiring alone, each digit of a combined pairing of bits defining a mutually exclusive binary quotient when said paired digits both have an active `1` value; and summing means associated with said wire shifting circuit for adding the combined binary quotients of the preselected bit pairs, whereby said wire shifting circuit adds the binary quotients of said preselected bit pairs without delay.
Claim 10
Dependent Claim
124 words
A hardware circuit for adding predetermined binary quotients associated with preselected digits of a given binary signal, each digit of said binary signal having a predetermined binary quotient associated therewith when having an active `1` value, said hardware circuit comprising: a wire shifting circuit wherein binary quotients associated with preselected pairs of said bits comprising said given binary signal are combined by wiring alone, each digit of a combined pairing of bits defining a mutually exclusive binary quotient when said paired digits both have an active `1` value; and summing means associated with said wire shifting circuit for adding the combined binary quotients of the preselected bit pairs, whereby said wire shifting circuit adds the binary quotients of said preselected bit pairs without delay.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |