Divide-by-five divider

Claim 1

A divider circuit for dividing an eleven bit number x having a hexadecimal representation (abc) 16 by five, where a is a three bit quantity, b is a four bit quantity and c is a four bit quantity, said divider circuit comprising a first stage comprising a first circuit for determining A=3*a and a second circuit for determining X=(a+b) where A is a four bit value and X is a five bit value, a second stage connected to said first stage comprising a third circuit for determining Y=3*X where Y is a six bit value, a fourth circuit for determining B=A+3X 4 where B is a four bit value and X 4 is the fifth bit of X, and a fifth circuit for determining Z=(X+c)/5, where z is a three bit value, and for generating a residue R equal to x mod 5, and a third stage connected to said second stage comprising a sixth circuit for determining W=B+Y 4-5 where W is a four bit vale and Y 4-5 is the fifth and sixth bits of Y, a seventh circuit for determining Y 0-2 +Z=Q 0-2 where Y 0-2 are the first, second and third bits of Y and Q 0-2 are the first, second and third bits of an eight bit quotient Q, and for determining a carry bit H, and an eight circuit for determining Q 3-7 =W 0-3 +Y 3 +H where Q 3-7 are the fourth through eight bits of the quotient Q, and Y 3 is the fourth bit of Y, said divider circuit forming part of an address generator for generating addresses for a frame buffer for a video display system.