Rail-to-rail opamp with large sourcing current and small quiescent current

Claim 2

A CMOS operational amplifier coupled between a first and a second power supply rail, and having differential inputs and an output, comprising: an input circuit having a differential pair input stage coupled to the operational amplifier differential inputs, and a folded rail-to-rail second stage with an output; a negative slew detector having an input and an output, with said input coupled to said input circuit output; a buffer circuit having an input coupled to said negative slew detector output; and an output stage coupled to said buffer circuit and said negative slew detector, with an output coupled to the operational amplifier output.

Claim 3

The CMOS operational amplifier of claim 1 wherein said negative slew detector comprises: a source follower transistor having a gate terminal coupled to said input circuit output; a current source load transistor coupling a source terminal of said source follower transistor to the first power supply rail; a diode-connected transistor coupling a drain terminal of said source follower transistor to the second power supply rail; a current mirroring transistor having a gate terminal coupled to a gate and drain of said diode-connected transistor; and a load transistor having a gate terminal coupled to a gate terminal of said current source load transistor, and coupling said detector output at a drain of said current mirroring transistor to the first power supply rail; wherein, during negative slewing, a signal at said source follower transistor gate terminal moves close to the first power supply rail turning off said current source load transistor, and pulling said detector output close to the first power supply rail.

Claim 4

The CMOS operational amplifier of claim 2 wherein said output stage comprises: a first pull-up transistor having a gate terminal coupled to said source follower transistor source terminal, and a drain terminal coupled to the operational amplifier output; and a pull-down transistor having a gate terminal coupled to a non-inverting output of said buffer circuit, and a drain terminal coupled to the operational amplifier output.

Claim 5

The CMOS operational amplifier of claim 3 wherein said buffer circuit comprises a plurality of inverters coupled in series.

Claim 6

The CMOS operational amplifier of claim 4 wherein said output stage further comprises a second pull-up transistor having a drain terminal coupled to said first pull-up transistor gate terminal, and a gate terminal coupled to an inverting output of said buffer circuit.

Claim 7

The CMOS operational amplifier of claim 3 further comprising a unity gain buffer circuit coupling said source terminal of said source follower transistor to said gate terminal of said first pull-up transistor.

Claim 8

The CMOS operational amplifier of claim 6 wherein said unity gain buffer circuit comprises: an emitter follower bipolar transistor having an emitter terminal coupled to said gate terminal of said first pull-up transistor, a base terminal coupled to said source follower transistor source terminal, and a collector terminal coupled to the second power supply rail; a clamp bipolar transistor having an emitter terminal coupled to said source follower transistor source terminal, a base terminal coupled to said emitter follower emitter terminal, and a collector terminal coupled to said second power supply rail; and a current source load transistor coupling said emitter follower emitter terminal to the first power supply rail.

Claim 9

The CMOS operational amplifier of claim 1 further comprising a preamplifier stage coupled to said input circuit inputs to increase an overall gain of the CMOS operational amplifier.

Claim 10

The CMOS operational amplifier of claim 1 wherein said differential pair input stage further comprises source degeneration resistors.

Claim 11

A CMOS operational amplifier coupled between a first and a second power supply rail, and having differential inputs and an output, comprising: an input circuit including: a differential pair input stage having a pair of input transistors coupled to the operational amplifier differential inputs, respectively, and a pair of diode-connected load transistors, a folded rail-to-rail second stage having a pair of current mirroring transistors coupled to said diode-connected load transistors, respectively, and a pair of current mirroring pull-up transistors; a negative slew detector including: a source follower transistor having a gate terminal coupled to an output of said input circuit, a current source load transistor coupling a source terminal of said source follower transistor to the first power supply rail, a diode-connected transistor coupling a drain terminal of said source follower transistor to the second power supply rail, a current mirroring transistor having a gate terminal coupled to a gate and drain of said diode-connected transistor, and a load transistor having a gate terminal coupled to a gate terminal of said current source load transistor, and coupling said detector output at a drain of said current mirroring transistor to the first power supply rail; a buffer circuit having an input coupled to said negative slew detector output and coupled to a plurality of inverters, with said plurality of inverters coupled in series, said buffer circuit having a pair of inverting and non-inverting outputs; and an output stage including: a first pull-up transistor having a gate terminal coupled to said source follower transistor source terminal, and a drain terminal coupled to the operational amplifier output, and a pull-down transistor having a gate terminal coupled to said buffer circuit non-inverting output, and a drain terminal coupled to the operational amplifier output.

Claim 12

A CMOS operational amplifier coupled between a first and a second power supply rail, and having differential inputs and an output, comprising: an input circuit including: a differential pair input stage having a pair of input transistors coupled to the operational amplifier differential inputs, respectively, and a pair of diode-connected load transistors, a folded rail-to-rail second stage having a pair of current mirroring transistors coupled to said diode-connected load transistors, respectively, and a pair of current mirroring pull-up transistors; a negative slew detector including: a source follower transistor having a gate terminal coupled to an output of said input circuit, a current source load transistor coupling a source terminal of said source follower transistor to the first power supply rail, a diode-connected transistor coupling a drain terminal of said source follower transistor to the second power supply rail, a current mirroring transistor having a gate terminal coupled to a gate and drain of said diode-connected transistor, and a load transistor having a gate terminal coupled to a gate terminal of said current source load transistor, and coupling said detector output at a drain of said current mirroring transistor to the first power supply rail; a buffer circuit having an input coupled to said negative slew detector output and coupled to a plurality of inverters, with said plurality of inverters coupled in series, said buffer circuit having a pair of inverting and non-inverting outputs; and an output stage including: a first pull-up transistor having a gate terminal coupled to said source follower transistor source terminal, and a drain terminal coupled to the operational amplifier output, and a pull-down transistor having a gate terminal coupled to said buffer circuit non-inverting output, and a drain terminal coupled to the operational amplifier output.

Claim 13

The CMOS operational amplifier of claim 10 wherein said output stage further comprises a second pull-up transistor having a gate terminal coupled to said buffer circuit inverting output, and a drain terminal coupled to said first pull-up transistor gate terminal.