US5315069A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electromagnetic radiation reduction technique using grounded conductive traces circumscribing internal planes of printed circuit boards
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-10-02
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Granted: 1994-05-24
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Expires: 2012-10-02
Abstract
Abstract An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.
Inventors
- 👤 Ghassan R. Gebara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:16
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/0218; H05K9/00; H05K9/0007; H05K9/002; H05K9/0039; H05K1/0219; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/0929; H05K2201/093
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
309 words
A printed circuit board, comprising: a plurality of layers, each said layer having an inner component area circumscribed by a border area, wherein one of said layers is a ground plane, one of said layers is a power plane, and at least one of said layers is a signal layer; each layer including a plurality of conductive vias penetrating said layer, said conductive vias being located between said inner component area and said border area of each said layer, wherein said conductive vias define a circuitous path circumscribing said inner component area of each said layer and wherein said layers are stacked together so that each one of said plurality of conductive vias are aligned and in conductive contact with corresponding conductive vias of every other one of said plurality of layers; said ground plane including a conductive portion covering part of the inner component area of said ground plane, said conductive portion of said ground plane also extending to and electrically coupling to each of said plurality of conductive vias; each said signal layer including a conductive trace routed between said border area and said inner component area of said signal layer, said signal layer conductive trace generally following said circuitous path and electrically connecting to each of said conductive vias to circumscribe the inner component area of said signal layer; and said power plane including a conductive portion covering part of said power plane inner component area, and also including a conductive trace routed between said border area and said inner component area of said power plane, said power plane conductive trace generally following said circuitous path and electrically connecting to each of said vias to circumscribe the inner component area of said power plane, said power plane further including a nonconductive electrical isolation path between said power plane conductive portion and said power plane conductive trace.
Claim 2
Dependent Claim
309 words
A printed circuit board, comprising: a plurality of layers, each said layer having an inner component area circumscribed by a border area, wherein one of said layers is a ground plane, one of said layers is a power plane, and at least one of said layers is a signal layer; each layer including a plurality of conductive vias penetrating said layer, said conductive vias being located between said inner component area and said border area of each said layer, wherein said conductive vias define a circuitous path circumscribing said inner component area of each said layer and wherein said layers are stacked together so that each one of said plurality of conductive vias are aligned and in conductive contact with corresponding conductive vias of every other one of said plurality of layers; said ground plane including a conductive portion covering part of the inner component area of said ground plane, said conductive portion of said ground plane also extending to and electrically coupling to each of said plurality of conductive vias; each said signal layer including a conductive trace routed between said border area and said inner component area of said signal layer, said signal layer conductive trace generally following said circuitous path and electrically connecting to each of said conductive vias to circumscribe the inner component area of said signal layer; and said power plane including a conductive portion covering part of said power plane inner component area, and also including a conductive trace routed between said border area and said inner component area of said power plane, said power plane conductive trace generally following said circuitous path and electrically connecting to each of said vias to circumscribe the inner component area of said power plane, said power plane further including a nonconductive electrical isolation path between said power plane conductive portion and said power plane conductive trace.
Claim 3
Dependent Claim
20 words
The printed circuit board of claim 1, wherein said plurality of conductive vias are spaced approximately one quarter inch apart.
Claim 4
Dependent Claim
25 words
The printed circuit board of claim 1, wherein said plurality of conductive vias are approximately 18 milliinches in diameter filled with an electrically conductive material.
Claim 5
Dependent Claim
18 words
The printed circuit board of claim 1, wherein said signal layer conductive trace is approximately 30 milliinches wide.
Claim 6
Dependent Claim
18 words
The printed circuit board of claim 1, wherein said power plane conductive trace is approximately 60 milliinches wide.
Claim 7
Dependent Claim
28 words
The printed circuit board of claim 1, wherein said power plane, said ground plane and each of said signal layers are internal layers of the printed circuit board.
Claim 8
Dependent Claim
37 words
The printed circuit board of claim 1, wherein the conductive portions including said ground plane conductive portion, said signal layer conductive trace, said power plane conductive portion and said power plane conductive trace are formed of copper.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |