US5313430A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power down circuit for testing memory arrays
Assignee: International Business Machines Corp
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Filing: 1992-12-09
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Granted: 1994-05-17
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Expires: 2012-12-09
Abstract
Abstract A power down circuit for a default detection circuit, for detecting defects in memory array cells, comprising means for diverting the memory array standby current around the memory array cells to achieve the maximum ratio of change in input voltage as compared to the change in cell standby current and to provide improved tracking of the memory array over statistical variations of temperature, power supplies, process and other variables.
Inventors
- 👤 John R. Rawlins
- 👤 Carlos G. Rivadeneira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:58
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C8/00; G11C8/18; G11C2029/5006
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
126 words
A fault detection circuit for locating defective memory array cells, comprising: at least one pair of current busses, wherein the first bus functions as a word-line bus and the second bus functions as a drain-line bus; a plurality of parallel IC memory array cells coupled across the busses, whereby a standby current is provided at the word-line bus for the memory array; a word decoder coupled across the word-line and drain-line busses, and a word driver coupled to the word-line bus, which jointly provide word-line selection in the memory array cells; means for varying the array memory cell standby current in a power down operation; and means for diverting said standby current around the memory array cells to said drain-line bus during the power down operation.
Claim 2
Dependent Claim
126 words
A fault detection circuit for locating defective memory array cells, comprising: at least one pair of current busses, wherein the first bus functions as a word-line bus and the second bus functions as a drain-line bus; a plurality of parallel IC memory array cells coupled across the busses, whereby a standby current is provided at the word-line bus for the memory array; a word decoder coupled across the word-line and drain-line busses, and a word driver coupled to the word-line bus, which jointly provide word-line selection in the memory array cells; means for varying the array memory cell standby current in a power down operation; and means for diverting said standby current around the memory array cells to said drain-line bus during the power down operation.
Claim 3
Dependent Claim
46 words
The fault detection circuit of claim 1, wherein the means for diverting the standby current around the memory array cells is comprised of a series transistor - resistor circuit coupled across the word-line and drain-line busses in parallel relation to the plurality of memory array cells.
Claim 4
Dependent Claim
54 words
The fault detection circuit of claim 2, wherein the means for varying the standby current is a power down generator which is responsive to a power down input analog voltage to control the conductivity of the transistor in the diverting circuit to effect a reduction in the standby current during the power down operation.
Claim 5
Dependent Claim
51 words
The fault detection circuit of claim 3, wherein a power down driver circuit is used in the circuit between the power down generator and the current diverter means to assure that the same change in current as seen at the power down generator circuit is transmitted to the array standby cells.
Claim 6
Dependent Claim
73 words
The fault detection circuit of claim 4, wherein duplicated drain-line drivers are provided in the power down generator, the power down driver and the word decoder in order to assure that all the circuits will track to control the standby current across the entire memory array, in such a way that one can alter the memory cell standby current in the array from full cell standby current to a fully powered down state.
References Cited (Backward Citations)
US4553225A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |