Patent US5313422A successfully refreshed from Google Patents.
US5313422A
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Digitally controlled delay applied to address decoder for write vs. read
Assignee: Texas Instruments Inc
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Filing: 1991-05-29
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Granted: 1994-05-17
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Expires: 2011-05-29
Abstract
Abstract A digitally controlled asymmetrical delay circuit (DCADC) is described in which the amount of delay for an input transitioning in one direction (e.g. low to high) is controlled independently from the amount of delay for the input signal transitioning in the opposite direction (high to low). This digitally controlled asymmetrical delay circuit is applied to a memory address decode circuit. The DCADC is controlled by the WRITE/READ signal such that there is minimal delay when the WRITE signal is low (the READ signal is high), minimizing the delay introduced in the access time. When the WRITE signal is high (the READ signal is low), extra delay is added to the selection relative to the deselection of a memory location. In this manner, input noise during a WRITE is filtered out without slowing the access time.
Inventors
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:12
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
92 words
An address buffer circuit, having a digitally controlled delay comprising: a first logic circuit, connected to receive an address signal input; a second logic circuit, having a digital WRITE/READ control signal input; a delay circuit wherein said delay circuit output is coupled to said second logic circuit, and wherein said address signal is coupled to said delay circuit, and; wherein the output of said second logic circuit is coupled to said first logic circuit and wherein further said address signal is an output signal from an address pre-decode circuitry in a memory.
Claim 2
Dependent Claim
92 words
An address buffer circuit, having a digitally controlled delay comprising: a first logic circuit, connected to receive an address signal input; a second logic circuit, having a digital WRITE/READ control signal input; a delay circuit wherein said delay circuit output is coupled to said second logic circuit, and wherein said address signal is coupled to said delay circuit, and; wherein the output of said second logic circuit is coupled to said first logic circuit and wherein further said address signal is an output signal from an address pre-decode circuitry in a memory.
Claim 3
Dependent Claim
16 words
The address buffer circuit of claim 1, wherein said first logic circuit drives an address decoder.
Claim 4
Dependent Claim
15 words
The address buffer circuit of claim 1, wherein said logic circuit is a NAND circuit.
Claim 5
Dependent Claim
16 words
The address buffer circuit of claim 1, wherein said delay circuit is at least one inverter.
Claim 6
Dependent Claim
15 words
The address buffer circuit of claim 1, wherein said logic circuit is a NOR circuit.
Claim 7
Dependent Claim
16 words
The address buffer circuit of claim 1, wherein said delay circuit is an asymmetrical delay circuit.
Claim 8
Dependent Claim
86 words
A digitally controlled delay circuit comprised of: a first logic circuit, for driving a memory access circuit, connected to receive an input signal, wherein said input signal is an output from predecode circuitry; a second logic circuit, connected to receive a digital control signal; a delay circuit wherein said delay circuit output is coupled to said second logic circuit, and wherein said input signal is coupled to said delay circuit, and; wherein the output of said second logic circuit is coupled to said first logic circuit.
Claim 9
Dependent Claim
86 words
A digitally controlled delay circuit comprised of: a first logic circuit, for driving a memory access circuit, connected to receive an input signal, wherein said input signal is an output from predecode circuitry; a second logic circuit, connected to receive a digital control signal; a delay circuit wherein said delay circuit output is coupled to said second logic circuit, and wherein said input signal is coupled to said delay circuit, and; wherein the output of said second logic circuit is coupled to said first logic circuit.
Claim 10
Dependent Claim
19 words
The digitally controlled delay circuit of claim 7, wherein said digitally controlled delay circuit is an asymmetrical delay circuit.
Claim 11
Dependent Claim
19 words
The digitally controlled delay circuit of claim 7, wherein at least said first logic circuit is a NAND circuit.
Claim 12
Dependent Claim
17 words
The digitally controlled delay circuit of claim 7, wherein said delay circuit is at least one inverter.
Claim 13
Dependent Claim
19 words
The digitally controlled delay circuit of claim 7, wherein at least said first logic circuit is a NOR circuit.
Claim 14
Dependent Claim
24 words
The digitally controlled delay circuit of claim 7, wherein said digital control signal selectively enables a delay in the selection of a memory cell.
Claim 15
Dependent Claim
18 words
The digitally controlled delay circuit of claim 7, wherein said digital control signal is a WRITE/READ enable signal.
Claim 16
Dependent Claim
23 words
The digitally controlled delay circuit of claim 7, wherein said output of said first logic circuit is coupled to an address decode circuit.
Claim 17
Dependent Claim
20 words
The digitally controlled asymmetrical delay circuit of claim 12, wherein said enabled delay is greater during WRITE than during READ.
Claim 18
Independent Claim
120 words
The method of forming an address buffer circuit, having a digitally controlled delay, comprising the steps of: providing an input signal to a predecode circuit for generating an address signal; providing a WRITE/READ signal; applying said address signal to a delay circuit and one input of a first, at least two input, logic device; applying said WRITE/READ signal to one input of a second, at least two input, logic device; applying the output of said delay circuit to a second input of said second logic device; applying the output of said second logic device to a second input of said first logic device, and; applying the output of said first logic device to circuitry for selection of a memory element.
Claim 19
Independent Claim
120 words
The method of forming an address buffer circuit, having a digitally controlled delay, comprising the steps of: providing an input signal to a predecode circuit for generating an address signal; providing a WRITE/READ signal; applying said address signal to a delay circuit and one input of a first, at least two input, logic device; applying said WRITE/READ signal to one input of a second, at least two input, logic device; applying the output of said delay circuit to a second input of said second logic device; applying the output of said second logic device to a second input of said first logic device, and; applying the output of said first logic device to circuitry for selection of a memory element.
References Cited (Backward Citations)
US4656612A
Cited
US5014245A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |