Patent US5313084A successfully refreshed from Google Patents.
US5313084A
Expired / Lapsed
US
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Interconnect structure for an integrated circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1992-05-29
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Granted: 1994-05-17
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Expires: 2012-05-29
Abstract
Abstract A local interconnect structure for an integrated circuit is formed from a patterned refractory metal silicide. The local interconnect has an overlying oxide layer, which prevents part of the amorphous silicon used to form the interconnect from becoming silicided. This results in a local interconnect layer which has thinner silicide portions than silicide regions formed over adjacent source/drain regions and gate electrodes.
Inventors
- 👤 Che-Chia Wei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:09
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/0698
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
142 words
An interconnect structure for an integrated circuit, comprising: a semiconductor substrate; a source/drain region within the substrate; a field oxide region covering a portion of a surface of the substrate adjacent the source/drain region; a conductive electrode lying on a portion of the field oxide region; a local interconnect layer contacting the source drain region and the conductive electrode on the field oxide region, wherein the local interconnect layer is formed from a refractory metal silicide and has a relatively uniform thickness throughout; a silicon buffer layer overlying and directly contacting the local interconnect layer and co-extensive therewith; an oxide layer overlying and directly contacting the buffer layer and co-extensive therewith; and refractory metal silicide regions overlying the source/drain region and the conductive electrode, wherein such refractory metal silicide regions have a thickness greater than the thickness of the local interconnect layer.
Claim 2
Dependent Claim
142 words
An interconnect structure for an integrated circuit, comprising: a semiconductor substrate; a source/drain region within the substrate; a field oxide region covering a portion of a surface of the substrate adjacent the source/drain region; a conductive electrode lying on a portion of the field oxide region; a local interconnect layer contacting the source drain region and the conductive electrode on the field oxide region, wherein the local interconnect layer is formed from a refractory metal silicide and has a relatively uniform thickness throughout; a silicon buffer layer overlying and directly contacting the local interconnect layer and co-extensive therewith; an oxide layer overlying and directly contacting the buffer layer and co-extensive therewith; and refractory metal silicide regions overlying the source/drain region and the conductive electrode, wherein such refractory metal silicide regions have a thickness greater than the thickness of the local interconnect layer.
Claim 3
Dependent Claim
12 words
The structure of claim 1, wherein the buffer layer comprises amorphous silicon.
Claim 4
Dependent Claim
18 words
The structure of claim 1, wherein the source/drain region is a source/drain region of a field effect transistor.
Claim 5
Dependent Claim
21 words
The structure of claim 1, wherein the conductive electrode comprises a portion of a gate electrode for a field effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |