US5312769A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a semiconductor memory device
Assignee: Panasonic Holdings Corp
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Filing: 1993-04-13
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Granted: 1994-05-17
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Expires: 2013-04-13
Abstract
Abstract A semiconductor memory device in which a storage electrode of a storage capacitor of a memory cell is formed by a selective chemical vapor deposition (CVD) technique. A lithography process is not required when forming the storage electrode. There is no narrowing of the storage electrode pattern and the minimum distance between adjacent storage electrodes can be made smaller than the minimum wiring dimension. The storage capacitance of the semiconductor memory device can be increased and a high storage capacitance is obtained.
Inventors
- 👤 Naoto Matsuo
- 👤 Shouzou Okada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:06
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10B12/30; H10B12/48; H10D; H10D1/00; H10D1/60; H10D1/68
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
219 words
A method of fabricating a semiconductor memory device comprising the steps of: forming transistors on a semiconductor substrate; forming polycrystalline silicon lead pads on said semiconductor substrate, each of said polycrystalline silicon lead pads electrically connected to said transistors; forming a first interlayer insulating film over said transistors and said polycrystalline silicon lead pads; forming bit lines electrically connected to said transistors; forming a second interlayer insulating film on said bit lines; forming contact holes in said first interlayer insulating film, for exposing surfaces of said polycrystalline silicon lead pads; selectively growing first polycrystalline silicon films on said surfaces of said first polycrystalline silicon lead pads, and laterally growing upper portions of said polycrystalline silicon films, by a selective chemical vapor deposition technique, thereby forming lower portions of storage electrodes; forming oxide films on top and side surfaces of said lower portions of said storage electrodes; anisotropically etching said oxide films, for leaving portions of said oxide films on said side surfaces of said storage electrodes; selectively growing second polycrystalline silicon films on said top surfaces of said first polycrystalline silicon films by a selective chemical vapor deposition technique, thereby forming upper portions of said storage electrodes; removing said portions of said oxide films; forming dielectric films on said storage electrodes; and forming plate electrodes on said dielectric films.
Claim 2
Independent Claim
219 words
A method of fabricating a semiconductor memory device comprising the steps of: forming transistors on a semiconductor substrate; forming polycrystalline silicon lead pads on said semiconductor substrate, each of said polycrystalline silicon lead pads electrically connected to said transistors; forming a first interlayer insulating film over said transistors and said polycrystalline silicon lead pads; forming bit lines electrically connected to said transistors; forming a second interlayer insulating film on said bit lines; forming contact holes in said first interlayer insulating film, for exposing surfaces of said polycrystalline silicon lead pads; selectively growing first polycrystalline silicon films on said surfaces of said first polycrystalline silicon lead pads, and laterally growing upper portions of said polycrystalline silicon films, by a selective chemical vapor deposition technique, thereby forming lower portions of storage electrodes; forming oxide films on top and side surfaces of said lower portions of said storage electrodes; anisotropically etching said oxide films, for leaving portions of said oxide films on said side surfaces of said storage electrodes; selectively growing second polycrystalline silicon films on said top surfaces of said first polycrystalline silicon films by a selective chemical vapor deposition technique, thereby forming upper portions of said storage electrodes; removing said portions of said oxide films; forming dielectric films on said storage electrodes; and forming plate electrodes on said dielectric films.
Claim 3
Dependent Claim
39 words
A method of fabricating a semiconductor memory device according to claim 1, wherein said selective growth of at least one of said first and second polycrystalline silicon films is performed at a temperature from 650° C. to 800° C.
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US5128273A
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JPH01241857A
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JPH0219264A
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JPH0281655A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |