US5311521A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for implementing post-modulation error correction coding scheme
Assignee: RESEARCH Corp TECHNOLOGIES Inc A NOT-FOR-PROFIT NON-STOCK CORP OF
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Filing: 1990-01-12
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Granted: 1994-05-10
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Expires: 2010-01-12
Abstract
Abstract A method of and apparatus for providing error correction coding for a block of user data in which the user data is initially modulated by a first modulator and then the modulated user data is error correction encoded to produce a first plurality of check bits. The first plurality of check bits are then modulated by a second modulator whose output is then fed to a second error correction encoder which produces a second plurality of check bits. The modulated user data, the first plurality of check bits and the second plurality of check bits are all fed to a shift register where the error correction encoded user data block is formed, useful with magnetic and optical storage devices.
Inventors
- 👤 Boris Fitingof
- 👤 Masud Mansuripur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:53
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046; G11B20/10055; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426; G11B20/18; G11B20/1806; G11B20/1809
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
135 words
A method of providing burst error correction coding for a block of user data of length N, comprising the steps of: inputting said block of user data into a first shift register having a plurality of blocks of length k, said shift register having a total length N; generating a k plurality of parity bits using the user data from each of the plurality of blocks of length k; separately modulating and error correction coding each one of said plurality of blocks of length k and said k plurality of parity bits; and assembling a burst error correction coded block of user data by storing the results from modulation error correction coding said plurality of blocks of length k and said k plurality of parity bits sequentially following each other in a second shift register.
Claim 2
Independent Claim
135 words
A method of providing burst error correction coding for a block of user data of length N, comprising the steps of: inputting said block of user data into a first shift register having a plurality of blocks of length k, said shift register having a total length N; generating a k plurality of parity bits using the user data from each of the plurality of blocks of length k; separately modulating and error correction coding each one of said plurality of blocks of length k and said k plurality of parity bits; and assembling a burst error correction coded block of user data by storing the results from modulation error correction coding said plurality of blocks of length k and said k plurality of parity bits sequentially following each other in a second shift register.
Claim 3
Dependent Claim
40 words
The method of claim 1, wherein said step of generating a k plurality of parity bits using said user data from each of said plurality of blocks of length k utilizes one bit from each of said plurality of blocks.
Claim 4
Independent Claim
131 words
A method of providing burst error correction coding for a block of user data of length N, comprising the steps of: modulating and error correction coding said block of user data of length N to produce a coded data block; inputting said coded data block into a first shift register having a plurality of blocks of length k, said shift register having a length N; generating a k plurality of parity bits using the contents from each of the plurality of blocks of length k; modulating and error correction coding said k plurality of parity bits; and storing said modulated and error correction coded k plurality of bits following said coded data block as contents of a second shift register, thus forming a block of burst error correction coded user data.
Claim 5
Independent Claim
131 words
A method of providing burst error correction coding for a block of user data of length N, comprising the steps of: modulating and error correction coding said block of user data of length N to produce a coded data block; inputting said coded data block into a first shift register having a plurality of blocks of length k, said shift register having a length N; generating a k plurality of parity bits using the contents from each of the plurality of blocks of length k; modulating and error correction coding said k plurality of parity bits; and storing said modulated and error correction coded k plurality of bits following said coded data block as contents of a second shift register, thus forming a block of burst error correction coded user data.
Claim 6
Dependent Claim
39 words
The method of claim 3, wherein said step of generating a k plurality of parity bits using the contents from each of the plurality of blocks of length k utilizes one bit from each of said plurality of blocks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-09 | 1997-11-08 | 1998-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-09 | 2001-11-08 | 2002-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-09 | 2005-11-08 | 2006-05-10 | $7700.00 | Window Closed / Lapsed |