Abstract A circuit for compressing and expanding video data comprises a FIFO line memory and an interpolator. A timing circuit generates control signals for writing data into the line memory and for reading data from the line memory to compress and expand the data. The interpolator smooths the data expanded or to be compressed in the FIFO line memory. A switching network selectively establishes a first signal path in which the line memory precedes the interpolator for implementing the data expansion and a second signal path in which the interpolator precedes the line memory for implementing the data compression. The switching network is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.
A signal processing circuit, comprising: a line memory; means for generating control signals for writing data into said line memory and for reading data from said line memory to compress and expand said data; an interpolator for smoothing data expanded or to be compressed in said line memory; and, a switching network for selectively establishing a first signal path in which said line memory precedes said interpolator for implementing said data expansion and a second signal path in which said interpolator precedes said line memory for implementing said data compression.
Claim 2
Dependent Claim
90 words
A signal processing circuit, comprising: a line memory; means for generating control signals for writing data into said line memory and for reading data from said line memory to compress and expand said data; an interpolator for smoothing data expanded or to be compressed in said line memory; and, a switching network for selectively establishing a first signal path in which said line memory precedes said interpolator for implementing said data expansion and a second signal path in which said interpolator precedes said line memory for implementing said data compression.
Claim 3
Dependent Claim
13 words
The circuit of claim 1, further comprising means for controlling said switching network.
Claim 4
Dependent Claim
24 words
The circuit of claim 1, wherein said line memory is a first in first out (FIFO) device having independently enabled write and read ports.