US5311085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clocked comparator with offset-voltage compensation
Assignee: US Philips Corp
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Filing: 1992-04-13
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Granted: 1994-05-10
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Expires: 2012-04-13
Abstract
Abstract A clocked comparator circuit comprises an input stage and a sample-and-hold circuit and an amplifier-latch circuit coupled to the output of the input stage. The sample-and-hold circuit provides an accurate offset-voltage compensation and the amplifier-latch circuit provides a high operating speed by means of a switchable current source (S6, T11). Switches are provided so that the amplifier-latch circuit constitutes a differential load having a high positive impedance during a first state of a clock signal, a low positive impedance during a next state of the clock signal, and a negative impedance during a following state of the clock signal.
Inventors
- 👤 Marcellinus J. M. Pelgrom
- 👤 Antonia C. Van Rens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:49
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/249; G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
333 words
A comparator circuit for converting a voltage difference appearing between a first and a second input terminal of the comparator circuit during a first state of a clock signal into a voltage difference appearing between a first and a second output terminal during a second state of the clock signal, the comparator circuit comprising: an input differential amplifier having a non-inverting input and an inverting input and having an inverting output and a non-inverting output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling a voltage difference appearing between the first and the second input terminal during the first state of the clock signal to the non-inverting input and the inverting input respectively, a sample-and-hold circuit coupled to the inverting output and the non-inverting output of the input differential amplifier and comprising a further differential amplifier having a first input coupled to a first capacitor and a second input coupled to a second capacitor, and means coupling an amplifier-latch circuit to the inverting output and the non-inverting output of the input differential amplifier, the amplifier-latch circuit comprising a first pair of diode-connected transistors coupled between a first common node and the inverting output and the non-inverting output of the input differential amplifier, a second pair of cross-coupled transistors coupled between a second common node and the inverting output and the non-inverting output of the input differential amplifier, a current-mirror with a switchable current transfer having an input terminal coupled to the second common node and an output terminal, and further switching means for coupling the output terminal of the current-mirror to the first common node during the first and a third state of the clock signal and for switching the current transfer of the current mirror from a first transfer value to a second transfer value during at least the third state of the clock signal, wherein the third state of the clock signal occurs between the first and second clock signal states.
Claim 2
Dependent Claim
333 words
A comparator circuit for converting a voltage difference appearing between a first and a second input terminal of the comparator circuit during a first state of a clock signal into a voltage difference appearing between a first and a second output terminal during a second state of the clock signal, the comparator circuit comprising: an input differential amplifier having a non-inverting input and an inverting input and having an inverting output and a non-inverting output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling a voltage difference appearing between the first and the second input terminal during the first state of the clock signal to the non-inverting input and the inverting input respectively, a sample-and-hold circuit coupled to the inverting output and the non-inverting output of the input differential amplifier and comprising a further differential amplifier having a first input coupled to a first capacitor and a second input coupled to a second capacitor, and means coupling an amplifier-latch circuit to the inverting output and the non-inverting output of the input differential amplifier, the amplifier-latch circuit comprising a first pair of diode-connected transistors coupled between a first common node and the inverting output and the non-inverting output of the input differential amplifier, a second pair of cross-coupled transistors coupled between a second common node and the inverting output and the non-inverting output of the input differential amplifier, a current-mirror with a switchable current transfer having an input terminal coupled to the second common node and an output terminal, and further switching means for coupling the output terminal of the current-mirror to the first common node during the first and a third state of the clock signal and for switching the current transfer of the current mirror from a first transfer value to a second transfer value during at least the third state of the clock signal, wherein the third state of the clock signal occurs between the first and second clock signal states.
Claim 3
Dependent Claim
48 words
A comparator circuit as claimed in claim 1, wherein the first and second input of the further differential amplifier are coupled to the inverting and the non-inverting output of the input differential amplifier via second and third switching means, respectively, during the first state of the clock signal.
Claim 4
Dependent Claim
39 words
A comparator circuit as claimed in claim 2, wherein a first and a second output of the further differential amplifier of the sample-and-hold circuit are respectively coupled to the inverting and the non-inverting output of the input differential amplifier.
Claim 5
Dependent Claim
40 words
A comparator circuit as claimed in claim 3, further comprising fourth switching means for coupling a reference voltage to both the inverting input and the non-inverting input of the input differential amplifier during the third state of the clock signal.
Claim 6
Dependent Claim
40 words
A comparator circuit as claimed in claim 2, further comprising fourth switching means for coupling a reference voltage to both the inverting input and the non-inverting input of the input differential amplifier during the third state of the clock signal.
Claim 7
Dependent Claim
42 words
A comparator circuit as claimed in claim 1, wherein a reference voltage is coupled to both the inverting input and the non-inverting input of the input differential amplifier during the third state of the clock signal by means of a switching device.
Claim 8
Dependent Claim
233 words
A clocked comparator circuit for converting an input voltage at a first and a second input terminal during a first state of a clock signal into an output voltage appearing between a first and a second output terminal of the comparator circuit during a second state of the clock signal, the comparator circuit comprising: an input differential amplifier having a first input and a second input and having a first output and a second output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling an input voltage appearing between the first and the second input terminal to the first and second input, respectively, of the input differential amplifier during the first state of the clock signal, a sample-and-hold circuit comprising a further differential amplifier having a first input coupled to a first capacitor and a second input coupled to a second capacitor and second and third switching means for coupling said first and second input of the further differential amplifier to the first and second outputs of the input differential amplifier during the first state of the clock signal, and an amplifier-latch circuit coupled to the first and second outputs of the input differential amplifier, and wherein the amplifier-latch circuit comprises two diode-connected transistors coupled to a current source via fourth switching means and to a further current source via fifth switching means.
Claim 9
Dependent Claim
233 words
A clocked comparator circuit for converting an input voltage at a first and a second input terminal during a first state of a clock signal into an output voltage appearing between a first and a second output terminal of the comparator circuit during a second state of the clock signal, the comparator circuit comprising: an input differential amplifier having a first input and a second input and having a first output and a second output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling an input voltage appearing between the first and the second input terminal to the first and second input, respectively, of the input differential amplifier during the first state of the clock signal, a sample-and-hold circuit comprising a further differential amplifier having a first input coupled to a first capacitor and a second input coupled to a second capacitor and second and third switching means for coupling said first and second input of the further differential amplifier to the first and second outputs of the input differential amplifier during the first state of the clock signal, and an amplifier-latch circuit coupled to the first and second outputs of the input differential amplifier, and wherein the amplifier-latch circuit comprises two diode-connected transistors coupled to a current source via fourth switching means and to a further current source via fifth switching means.
Claim 10
Dependent Claim
57 words
A comparator circuit as claimed in claim 7 further comprising sixth switching means for coupling a reference voltage to both the first input and the second input of the input differential amplifier during a third state of the clock signal, wherein said third state follows the first state and precedes the second state of the clock signal.
Claim 11
Dependent Claim
54 words
A comparator circuit as claimed in claim 7 further comprising a current mirror including the current source and the further current source of the amplifier-latch circuit, and the amplifier-latch circuit further comprises a pair of cross-coupled transistors coupled to the current mirror circuit and the first and second outputs of the input differential amplifier.
Claim 12
Dependent Claim
216 words
A comparator circuit for converting, during a first state of a clock signal, an input voltage at a first and a second input terminal into an output voltage appearing between a first and a second output terminal of the comparator circuit during a second state of the clock signal, the comparator circuit comprising: an input differential amplifier having a first input and a second input and having a first output and a second output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling an input voltage appearing between the first and the second input terminal to the first and second input, respectively, of the input differential amplifier, a sample-and-hold circuit comprising a further differential amplifier coupled to first and second capacitors, an amplifier-latch circuit coupled to the first and second outputs of the input differential amplifier to form a load, and further switching means controlled by the clock signal so that the amplifier-latch circuit constitutes a load having a high positive impedance during the first state of the clock signal, a negative impedance during the second state of the clock signal, and a low positive impedance during a third state of the clock signal that occurs between the first and second states of the clock signal.
Claim 13
Dependent Claim
216 words
A comparator circuit for converting, during a first state of a clock signal, an input voltage at a first and a second input terminal into an output voltage appearing between a first and a second output terminal of the comparator circuit during a second state of the clock signal, the comparator circuit comprising: an input differential amplifier having a first input and a second input and having a first output and a second output coupled respectively to the first and the second output terminal of the comparator circuit, first switching means for coupling an input voltage appearing between the first and the second input terminal to the first and second input, respectively, of the input differential amplifier, a sample-and-hold circuit comprising a further differential amplifier coupled to first and second capacitors, an amplifier-latch circuit coupled to the first and second outputs of the input differential amplifier to form a load, and further switching means controlled by the clock signal so that the amplifier-latch circuit constitutes a load having a high positive impedance during the first state of the clock signal, a negative impedance during the second state of the clock signal, and a low positive impedance during a third state of the clock signal that occurs between the first and second states of the clock signal.
Claim 14
Dependent Claim
51 words
A comparator circuit as claimed in claim 10 wherein the amplifier-latch circuit further comprises two diode-connected transistors coupled to a first current source via a second switching means and to a further current source via a third switching means, wherein said second and third switching means comprise said further switching means.
Claim 15
Dependent Claim
38 words
A comparator circuit as claimed in claim 11 further comprising a reference voltage coupled to the first and second inputs of the input differential amplifier during the third state of the clock signal via a fourth switching means.
Claim 16
Dependent Claim
38 words
A comparator circuit as claimed in claim 10 further comprising a reference voltage coupled to the first and second inputs of the input differential amplifier during the third state of the clock signal via a second switching means.
Claim 17
Dependent Claim
53 words
A comparator circuit as claimed in 11 further comprising a current mirror including the current source and the further current source of the amplifier-latch circuit, and the amplifier-latch circuit further comprises a pair of cross-coupled transistors coupled to the current mirror circuit and the first and second outputs of the input differential amplifier.
Claim 18
Dependent Claim
79 words
A comparator circuit as claimed in claim 10 wherein the amplifier-latch circuit further comprises a pair of diode-connected transistors coupled in series with a second switching means and a current source between the first and second outputs of the input differential amplifier and a circuit node, and a third switching means for coupling said pair of diode-connected transistors to the circuit node via a second current source, wherein said second and third switching means comprise said further switching means.
Claim 19
Dependent Claim
57 words
A comparator circuit as claimed in claim 10 wherein the input differential amplifier further comprises first and second transistors coupled to a first terminal of a source of supply voltage via first and second current sources, respectively, and further connected in common via a third current source to a second terminal of said source of supply voltage.
Claim 20
Dependent Claim
62 words
A comparator circuit as claimed in claim 11 wherein during the first state of the clock signal the second switching means is closed and the third switching means is open, during the second state of the clock signal the second switching means is open and during the third state of the clock signal the second and third switching means are both closed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-09 | 1997-11-08 | 1998-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-09 | 2001-11-08 | 2002-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-09 | 2005-11-08 | 2006-05-10 | $7700.00 | Window Closed / Lapsed |