US5309447A
Expired / Lapsed
US
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Space compression technique for pseudo-exhaustive self-testing of digital electronic circuits
Assignee: Nokia Bell Labs
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Filing: 1991-06-03
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Granted: 1994-05-03
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Expires: 2011-06-03
Abstract
Abstract Compaction of the response signals produced by separate sets of sub-circuits (12 i ) within a digital circuit (10) under test is accomplished by first analyzing each response signal produced by a corresponding set of sub-circuits (by way of a logic analyzer (16,18)) to determine if the response signal has a particular pattern. A pattern bit is then set in accordance with the response signal which has the particular pattern. The pattern bits are then compacted by a set of daisy-chained time compactors (20), each compactor serving to exclusively OR the pattern bit from a corresponding logic analyzer (16,18) with a compacted bit generated previously by an upstream compactor.
Inventors
- 👤 Marsha R. Moskowitz
- 👤 Eleanor Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:03
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27; G06F11/28
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
124 words
A method for compacting a plurality of response signals, each generated by a separate set of sub-circuits within an electronic digital circuit under test, comprising the steps of: logically analyzing each response signal generated by each set of sub-circuits and generating a pattern bit indicative of whether that response signal has a particular pattern; time compacting each pattern bit of each set of sub-circuits by exclusively OR'ing it with a compacted bit generated previously by the same subset of circuits to yield a current compacted bit for subsequent exclusive OR'ing with a subsequently generated pattern bit associated with a different set of sub-circuits; and repeating the steps of logically analyzing each response signal and time-compacting each pattern bit for a predetermined number of times.
Claim 2
Independent Claim
124 words
A method for compacting a plurality of response signals, each generated by a separate set of sub-circuits within an electronic digital circuit under test, comprising the steps of: logically analyzing each response signal generated by each set of sub-circuits and generating a pattern bit indicative of whether that response signal has a particular pattern; time compacting each pattern bit of each set of sub-circuits by exclusively OR'ing it with a compacted bit generated previously by the same subset of circuits to yield a current compacted bit for subsequent exclusive OR'ing with a subsequently generated pattern bit associated with a different set of sub-circuits; and repeating the steps of logically analyzing each response signal and time-compacting each pattern bit for a predetermined number of times.
Claim 3
Dependent Claim
83 words
The method according to claim 1 wherein the step of logically analyzing the stream of response signals generated by each separate group of sub-circuits comprises the steps of: inverting selected bits in the stream of response signals; and applying each of the bits in the response signal, as selectively inverted, to a separate one of the inputs of a logic gate, which in response generates a pattern bit in accordance with the state of the bits in the response signal, as selectively inverted.
Claim 4
Dependent Claim
124 words
Apparatus for compacting a plurality of streams of response signals, each response signal produced by a separate set of sub-circuits within an electronic digital circuit under test, comprising: a plurality of logic-analyzing means, each serving to analyze the response signal generated by a separate set of sub-circuits and producing a response bit indicative of whether the response signal produced by the corresponding sub-circuit has a particular pattern; and a plurality of time-compaction means, each associated with each logic-analyzing means and connected in a daisy-chain fashion in a loop for producing a time-compacted bit in accordance with both the pattern bit from the corresponding logic-analyzing means connected thereto and with a time-compacted bit produced previously by a time-compaction means associated with another logic analyzer means.
Claim 5
Dependent Claim
124 words
Apparatus for compacting a plurality of streams of response signals, each response signal produced by a separate set of sub-circuits within an electronic digital circuit under test, comprising: a plurality of logic-analyzing means, each serving to analyze the response signal generated by a separate set of sub-circuits and producing a response bit indicative of whether the response signal produced by the corresponding sub-circuit has a particular pattern; and a plurality of time-compaction means, each associated with each logic-analyzing means and connected in a daisy-chain fashion in a loop for producing a time-compacted bit in accordance with both the pattern bit from the corresponding logic-analyzing means connected thereto and with a time-compacted bit produced previously by a time-compaction means associated with another logic analyzer means.
Claim 6
Dependent Claim
57 words
The apparatus according to claim 3 wherein each said logic-analyzing means comprises: means for selectively inverting selected bits of the response signal input to the logic-analyzing means; and a logic gate having a plurality of inputs, each input supplied with a corresponding one of the bits of the response signal, as selectively inverted by said inverting means.
Claim 7
Dependent Claim
81 words
The apparatus according to claim 3 wherein each said time-compaction means comprises: an exclusive OR gate having a first input supplied with the output of the logic-analyzing means associated with said time-compaction means, a second input supplied with the output of a first other time-compaction means and an output; and a flip-flop coupled to the output of said exclusive OR gate for storing the signal produced thereby and for supplying said signal at subsequent intervals to a second other time-compaction means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-02 | 1997-11-01 | 1998-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-02 | 2001-11-01 | 2002-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-02 | 2005-11-01 | 2006-05-03 | $7700.00 | Window Closed / Lapsed |