Patent US5309394A successfully refreshed from Google Patents.
US5309394A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single element security fusible link
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1993-09-08
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Granted: 1994-05-03
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Expires: 2013-09-08
Abstract
Abstract An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.
Inventors
- 👤 William J. Wuertz
- 👤 Steven K. Stefek
- 👤 William W. McKinley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:46
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
112 words
A method of using an I/O pad of an integrated circuit chip, with the I/O pad being connected to a logic circuit, and further with the integrated circuit chip having a memory connected to a write enable line, comprising the steps of: connecting a fuse between the I/O pad and the write enable line; applying a first voltage potential to the I/O pad so as to access the write enable line and allow data to be written to the memory; applying a second voltage potential to the I/O pad so as to blow the fuse and prevent access to the write enable line; and accessing the logic circuit through the I/O pad.
Claim 2
Independent Claim
112 words
A method of using an I/O pad of an integrated circuit chip, with the I/O pad being connected to a logic circuit, and further with the integrated circuit chip having a memory connected to a write enable line, comprising the steps of: connecting a fuse between the I/O pad and the write enable line; applying a first voltage potential to the I/O pad so as to access the write enable line and allow data to be written to the memory; applying a second voltage potential to the I/O pad so as to blow the fuse and prevent access to the write enable line; and accessing the logic circuit through the I/O pad.
Claim 3
Dependent Claim
21 words
The method of claim 1, wherein the second voltage potential applying step is performed after the first voltage potential applying step.
Claim 4
Dependent Claim
18 words
The method of claim 2, wherein the accessing step is performed after the second voltage potential applying step.
Claim 5
Dependent Claim
17 words
The method of claim 1, wherein the second voltage potential is greater than the first voltage potential.
Claim 6
Independent Claim
101 words
A method of using an I/O pad of an integrated circuit chip having a memory and a logic circuit, comprising the steps of: connecting a fuse between the I/O pad and a write enable line of the memory; accessing the write enable line through the I/O pad so as to allow data to be stored in the memory; applying a voltage potential to the I/O pad so as to blow the fuse and prevent further access to the write enable line; and accessing an I/O line of the logic circuit through the I/O pad so as to access the logic circuit.
Claim 7
Independent Claim
101 words
A method of using an I/O pad of an integrated circuit chip having a memory and a logic circuit, comprising the steps of: connecting a fuse between the I/O pad and a write enable line of the memory; accessing the write enable line through the I/O pad so as to allow data to be stored in the memory; applying a voltage potential to the I/O pad so as to blow the fuse and prevent further access to the write enable line; and accessing an I/O line of the logic circuit through the I/O pad so as to access the logic circuit.
Claim 8
Dependent Claim
20 words
The method of claim 5, wherein the voltage potential applying step is performed after the write enable line accessing step.
Claim 9
Dependent Claim
19 words
The method of claim 6, wherein the I/O line accessing step is performed after the voltage potential applying step.
Claim 10
Independent Claim
115 words
A method of using an I/O pad of an integrated circuit chip, with the I/O pad being connected to a logic circuit, and with the integrated circuit chip having a memory connected to a write enable line, and further with a fuse being connected between the I/O pad and the write enable line, comprising the steps of: applying a first voltage potential to the I/O pad so as to access the write enable line and allow data to be written to the memory; applying a second voltage potential to the I/O pad so as to blow the fuse and prevent access to the write enable line; and accessing the logic circuit through the I/O pad.
Claim 11
Independent Claim
115 words
A method of using an I/O pad of an integrated circuit chip, with the I/O pad being connected to a logic circuit, and with the integrated circuit chip having a memory connected to a write enable line, and further with a fuse being connected between the I/O pad and the write enable line, comprising the steps of: applying a first voltage potential to the I/O pad so as to access the write enable line and allow data to be written to the memory; applying a second voltage potential to the I/O pad so as to blow the fuse and prevent access to the write enable line; and accessing the logic circuit through the I/O pad.
Claim 12
Dependent Claim
21 words
The method of claim 8, wherein the second voltage potential applying step is performed after the first voltage potential applying step.
Claim 13
Dependent Claim
18 words
The method of claim 9, wherein the accessing step is performed after the second voltage potential applying step.
Claim 14
Dependent Claim
17 words
The method of claim 8, wherein the second voltage potential is greater than the first voltage potential.
References Cited (Backward Citations)
JPH02192093A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-02 | 1997-11-01 | 1998-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-02 | 2001-11-01 | 2002-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-02 | 2005-11-01 | 2006-05-03 | $7700.00 | Window Closed / Lapsed |