Semiconductor memory device

Claim 2

A semiconductor memory device including: a plurality of word lines; a plurality of switches each of which is controlled by a corresponding one of said plurality of word lines; and a plurality of information storage means each of which is coupled between a corresponding one of said plurality of switches and a reference potential, wherein a memory cell block includes a plurality of memory cells each of which comprises a corresponding one of said plurality of information storage means, a corresponding one of said plurality of switches and a corresponding one of said plurality of word lines, and wherein said plurality of switches of said plurality of memory cells are so connected in series that the information storage means of one of said plurality of memory cells is coupled between the switch of said one memory cell and the switch of the adjacent memory cell, wherein information of said information storage means of said one memory cell is read out on a signal terminal through said switch of said one memory cell and said switch of said adjacent memory cell, and wherein information is written into said information storage means of said one memory cell through said signal terminal, said switch of said adjacent memory cell and said switch of said one memory cell.

Claim 3

A semiconductor memory device according to claim 1, wherein said memory device includes a data-line coupled to said signal terminal, and wherein a plurality of said memory cell blocks are connected to said data-line.

Claim 4

A semiconductor memory device according to claim 2, wherein said plurality of memory cell blocks are connected to the data-line through signal transfer means, and wherein said signal transfer means transfers a signal in the reading operation in a state in which an input impedance from said memory cell blocks is high.

Claim 5

A semiconductor memory device according to claim 2, including therein a plurality of said data-lines to each of which said plurality of memory cell blocks are connected.

Claim 6

A semiconductor memory device according to claim 4, wherein said memory device includes a global data-line, and wherein said plurality of data-lines are connected to said global data-line through said signal transfer means.

Claim 7

A semiconductor memory device according to claim 5, including therein the plurality of global data-lines to each of which said plurality of data-lines is connected.

Claim 8

A semiconductor memory device according to claim 5, wherein said signal transfer means transfers a signal in the reading operation in a state in which an input impedance from said data-line is high, and acts as connection means in the writing operation.

Claim 9

A semiconductor memory device according to claim 2, wherein sense means for sensing a signal read out from said memory cell block is provided and said sense means is connected to said data-lines.

Claim 10

A semiconductor memory device according to claim 5, wherein sense means for sensing a signal read out from said memory cell block is provided and said sense means is connected to said global data-line.

Claim 11

A semiconductor memory device according to claim 8, including therein a register circuit for temporarily storing therein information sensed by said sense means.

Claim 12

A semiconductor memory device according to claim 10, wherein a storage capacity of said register circuit is substantially equal to a storage capacity of said memory cell block.

Claim 13

A semiconductor memory device according to claim 10, wherein a storage capacity of said register circuit is smaller than a storage capacity of said memory cell block by one storage means.

Claim 14

A semiconductor memory device according to claim 8, wherein the reading and writing operation is performed in such a way that information read out from a certain memory cell block is sensed by said sense means, and the sensed result is written to other memory cell block connected to the same data-line as that of said certain memory cell block.

Claim 15

A semiconductor memory device according to claim 13, wherein the number of memory cell blocks provided in said data-line is more than the number required for the storage capacity of said device by one per data-line.

Claim 16

A semiconductor memory device according to claim 13, comprising means for storing a correspondence relationship between said plurality of memory cell blocks and an address inputted from the external side of said device, and means for selecting a memory cell block in accordance with the correspondence relationship therebetween.

Claim 17

A semiconductor memory device according to claim 8, wherein said data-line is paired with another data-line, and differential signal sense means is connected to said pair of data-lines and sensing differential between signals of said paired data-lines.

Claim 18

A semiconductor memory device according to claim 9, wherein said global data-line is paired with another global data-line, and differential signal sense means is connected to said pair of global data-lines and sensing differential between signals of said data-lines.

Claim 19

A semiconductor memory device according to claim 4, including therein a dummy data-line provided in common in said plurality of data-lines, a plurality of signal converting means connected to said plurality of data-lines and said dummy data-line, respectively, and a plurality of differential signal sense means provided corresponding to the signal converting means provided in said plurality of data-lines, wherein an output of the signal converting means provided in each of said data-lines, and an output of the signal converting means provided in said dummy data-line are inputted to each of said differential signal sense means.

Claim 20

A semiconductor memory device according to claim 18, wherein said signal converting means is made up of signal transfer means comprised of a voltage-to-current converter cooperating with a load circuit acting as a current-to-voltage converter.

Claim 21

A semiconductor memory device according to claim 6, including therein a plurality of differential signal sense means provided in said plurality of global data-lines, and a global dummy data-line provided in common in said plurality of global data-lines, to which a plurality of dummy data-lines are connected by signal transfer means which is capable of being selected by a control signal, wherein each of said global data-lines and said global dummy data-line are connected to differential signal means provided in each of said global data-lines.

Claim 22

A semiconductor memory device according to claim 18, wherein a dummy cell block having the same arrangement as that of said memory cell block is connected to said dummy data-line.

Claim 23

A semiconductor memory device according to claim 21, wherein the number of dummy cell blocks connected to said dummy data-line is equal to the number of memory cell blocks connected to each of said data-lines, and said memory cell blocks and said dummy cell blocks are connected to the respective word-lines to which the same signal is applied.

Claim 24

A semiconductor memory device according to claim 4, wherein said signal converting means is provided in common in said plurality of data-lines and said plurality of dummy data-lines, and switch means is provided for connecting said signal converting means and each of said plurality of data-lines and said plurality of dummy data-lines to each other.

Claim 25

A semiconductor memory device according to claim 5, wherein said signal transfer means is provided in common in said plurality of data-lines and said plurality of dummy data-lines, and switch means is provided for connecting said signal transfer means and each of said plurality of data-lines and said plurality of dummy data-lines to each other.

Claim 26

A semiconductor memory device according to claim 1, wherein said memory cell block is arranged in such a way that one switch is constructed by one transistor and one storage means is constructed by one capacitor.

Claim 27

A semiconductor memory device according to claim 25, wherein said memory cell block is arranged by connecting a plurality of transistors in series in such a way that an impurity-doped region is shared between two transistors.

Claim 28

A semiconductor memory device according to claim 25, wherein said capacitor is made up of an electrode which is in contact with one impurity-doped region of said transistor and extends over said transistor and data-line, an insulating film provided on said electrode, and a conductive electrode provided on said insulating film.

Claim 29

A semiconductor memory device according to claim 25, wherein the number of storage means connected to said data-lines is six per connection hole of said data-lines.

Claim 30

A semiconductor memory device according to claim 25, wherein the number of storage means connected to said data-lines is four per connection hole of said data-lines.

Claim 31

A semiconductor memory device according to claim 25, wherein the number of storage means connected to said data-lines is two per connection hole of said data-lines.

Claim 32

A semiconductor memory device according to claim 1, wherein signal transfer of said device with external elements outside said semiconductor memory device is performed by a data transfer signal.

Claim 33

A semiconductor memory device according to claim 1 comprising a composing element used with a sound recording-reproducing apparatus comprising: voice input means for receiving and transmitting voice to an output signal; a first amplifier for amplifying an output signal from said voice input means and providing an output signal; an analog-to-digital converter for receiving and converting said output signal from said first amplifier to digital form and providing an output signal; a semiconductor memory for receiving and storing said output signal from said analog-to-digital converter and supplying an output signal; a digital-to-analog converter for being supplied with and converting said output signal from said semiconductor memory to analog signal and providing an output signal; a second amplifier for amplifying said output signal from said digital-to-analog converter and providing an output signal; and voice output means receiving said output signal from said second amplifier and outputting voice.

Claim 34

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines; and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines; wherein sense means for sensing a signal read out from said memory cell block is provided and said sense means is connected to said data-lines, and wherein said semiconductor memory device includes a register circuit for temporarily storing therein information sensed by said sense means.

Claim 35

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines; and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines; wherein sense means for sensing a signal read out from said memory cell block is provided and said sense means is connected to said data-lines, and wherein said semiconductor memory device includes a register circuit for temporarily storing therein information sensed by said sense means.

Claim 36

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines; and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines; wherein sense means for sensing a signal read out from said memory cell block is provided and said sense means is connected to said data-lines; and wherein the reading and writing operation is performed in such a way that information read out from a certain memory cell block is sensed by said sense means, and the sensed result is written to other memory cell block connected to the same data-line as that of said certain memory cell block.

Claim 37

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines; and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines; wherein sense means for sensing a signal read out from said memory cell block is provided and said sense means is connected to said data-lines; and wherein the reading and writing operation is performed in such a way that information read out from a certain memory cell block is sensed by said sense means, and the sensed result is written to other memory cell block connected to the same data-line as that of said certain memory cell block.

Claim 38

A semiconductor memory device according to claim 34, wherein the number of memory cell blocks provided in said data-line is more than the number required for the storage capacity of said device by one data-line.

Claim 39

A semiconductor memory device according to claim 34, comprising means for storing a correspondence relationship between said plurality of memory cell blocks and an address inputted from the external side of said device, and means for selecting a memory cell block in accordance with the correspondence relationship therebetween.

Claim 40

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines; and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines; wherein said plurality of memory cell blocks are connected to the data-line through signal transfer means, and said signal transfer means transfers a signal in the reading operation in a state in which an input impedance from said memory cell blocks is high; including therein a plurality of said data-lines to each of which said plurality of memory cell blocks are connected; including therein a dummy data-line provided in common in said plurality of data-lines, a plurality of signal converting means connected to said plurality of data-lines and said dummy data-line, respectively, and a plurality of differential signal sense means provided corresponding to the signal converting means provided in said plurality of data-lines, wherein an output of the signal converting means provided in each of said data-lines, and an output of the signal converting means provided in said dummy data-line are inputted to each of said differential signal sense means.

Claim 41

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines; and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said memory device includes a data-line, and a plurality of said memory cell blocks are connected to said data-lines; wherein said plurality of memory cell blocks are connected to the data-line through signal transfer means, and said signal transfer means transfers a signal in the reading operation in a state in which an input impedance from said memory cell blocks is high; including therein a plurality of said data-lines to each of which said plurality of memory cell blocks are connected; including therein a dummy data-line provided in common in said plurality of data-lines, a plurality of signal converting means connected to said plurality of data-lines and said dummy data-line, respectively, and a plurality of differential signal sense means provided corresponding to the signal converting means provided in said plurality of data-lines, wherein an output of the signal converting means provided in each of said data-lines, and an output of the signal converting means provided in said dummy data-line are inputted to each of said differential signal sense means.

Claim 42

A semiconductor memory device according to claim 37, wherein said signal converting means is made up of signal transfer means comprised of a voltage-to-current converter cooperating with a load circuit acting as a current-to-voltage converter.

Claim 43

A semiconductor memory device according to claim 38, wherein a dummy cell block having the same arrangement as that of said memory cell block is connected to said dummy data-lines.

Claim 44

A semiconductor memory device according to claim 39, wherein the number of dummy cell blocks connected to said dummy data-line is equal to the number of memory cell blocks connected to each of said data-lines, and said memory cell blocks and said dummy cell blocks are connected to the respective word-lines to which the same signal is applied.

Claim 45

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines, and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said memory device includes a data-line, and a plurality of said memory blocks are connected to said data-lines; wherein said plurality of memory cell blocks are connected to the data-line through signal transfer means, and said signal transfer means transfers a signal in the reading operation in a state in which an input impedance from said memory cell blocks is high; including therein a plurality of said data-lines to each of which said plurality of memory cell blocks are connected; wherein said signal converting means is provided in common in said plurality of data-lines and a plurality of dummy data-lines, and switch means is provided for connecting said signal converting means and each of said plurality of data-lines and said plurality of dummy data-lines to each other.

Claim 46

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines, and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises said switch and said information storage means, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said memory device includes a data-line, and a plurality of said memory blocks are connected to said data-lines; wherein said plurality of memory cell blocks are connected to the data-line through signal transfer means, and said signal transfer means transfers a signal in the reading operation in a state in which an input impedance from said memory cell blocks is high; including therein a plurality of said data-lines to each of which said plurality of memory cell blocks are connected; wherein said signal converting means is provided in common in said plurality of data-lines and a plurality of dummy data-lines, and switch means is provided for connecting said signal converting means and each of said plurality of data-lines and said plurality of dummy data-lines to each other.

Claim 47

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines; and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises a corresponding one of said plurality of information storage means, a corresponding one of said plurality of switches and a corresponding one of said plurality of word lines, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said capacitor is made up of an electrode which is in contact with one impurity-doped region of said transistor and extends over said transistor and data-line, an insulating film provided on said electrode, and a conductive electrode provided on said insulating film.

Claim 48

A semiconductor memory device including: a plurality of word-lines; a plurality of switches selected by said word-lines; and a plurality of information storage means being controlled of signal transfer by said switches, wherein a memory cell block is connected by connecting at least two memory cells each of which comprises a corresponding one of said plurality of information storage means, a corresponding one of said plurality of switches and a corresponding one of said plurality of word lines, in such a way that the switches are connected in series, and a signal of information storage means of a certain memory cell is read out through a switch of another memory cell in said memory cell block; wherein said capacitor is made up of an electrode which is in contact with one impurity-doped region of said transistor and extends over said transistor and data-line, an insulating film provided on said electrode, and a conductive electrode provided on said insulating film.