Symmetrical polarization enhancement in a ferroelectric memory cell

Claim 1

A ferroelectric memory, comprising: an array of memory cells, each cell having, a ferroelectric capacitor with a first plate and a second plate and ferroelectric material formed therebetween for storing either of two polarization states, a first isolation transistor for connecting the first plate of the ferroelectric capacitor to a drive line, and a second isolation transistor for connecting the second plate of the ferroelectric capacitor to a respective bit line, a word line address circuit for driving a gate terminal of the first and second isolation transistors of cells in a row; a drive line driver for driving a drive line connected to memory cells in the row, said drive line driver being adapted for driving the drive line with a first voltage level followed by a second, non-zero voltage level that has a magnitude less than the first voltage level; and wherein said word line address circuit terminates the drive to the gate terminals of the isolation transistors during a time period when the drive line is driven with the second voltage level, whereby the ferroelectric capacitors in an access row are polarized with a polarization state that is a function of a voltage of the respective bit line, and a voltage is isolated on either said first or second capacitor plate of the ferroelectric capacitors irrespective of a respective polarization state stored therein.

Claim 8

A method of writing a memory cell of the type having a ferroelectric capacitor as a storage element, comprising the steps of: accessing the memory cell by driving a first isolation transistor into conduction to connect a first plate of the ferroelectric capacitor to a drive line, and driving a second isolation transistor into conduction to connect a second plate of the ferroelectric capacitor to a bit line; driving the drive line with a voltage having a first amplitude while said first and second isolation transistors are conductive, and thereafter driving the drive line with a voltage having a second nonzero amplitude that is less than the first amplitude; and placing the first and second isolation transistors into cutoff during a time when the drive line is driven with said second amplitude voltage.

Claim 9

A method of writing a memory cell of the type having a ferroelectric capacitor as a storage element, comprising the steps of: accessing the memory cell by driving a first isolation transistor into conduction to connect a first plate of the ferroelectric capacitor to a drive line, and driving a second isolation transistor into conduction to connect a second plate of the ferroelectric capacitor to a bit line; driving the drive line with a voltage having a first amplitude while said first and second isolation transistors are conductive, and thereafter driving the drive line with a voltage having a second nonzero amplitude that is less than the first amplitude; and placing the first and second isolation transistors into cutoff during a time when the drive line is driven with said second amplitude voltage.

Claim 13

A method of writing to a ferroelectric cell of the type having a ferroelectric capacitor as a storage element, comprising the steps of: coupling a first plate of a ferroelectric capacitor to a drive line; coupling a second plate of the ferroelectric capacitor to a bit line; driving the bit line to one of a logic high or logic low voltage to polarize the ferroelectric capacitor to a desired polarization state; driving the drive line to a voltage having an amplitude that is intermediate the logic high and low voltage applied to the bit line; and isolating the first and second plates of the ferroelectric capacitor from the respective drive line and bit line while said drive line voltage and said bit line voltage are applied across the ferroelectric capacitor plates.

Claim 14

A method of writing to a ferroelectric cell of the type having a ferroelectric capacitor as a storage element, comprising the steps of: coupling a first plate of a ferroelectric capacitor to a drive line; coupling a second plate of the ferroelectric capacitor to a bit line; driving the bit line to one of a logic high or logic low voltage to polarize the ferroelectric capacitor to a desired polarization state; driving the drive line to a voltage having an amplitude that is intermediate the logic high and low voltage applied to the bit line; and isolating the first and second plates of the ferroelectric capacitor from the respective drive line and bit line while said drive line voltage and said bit line voltage are applied across the ferroelectric capacitor plates.

Claim 19

A method of enhancing polarization states in a ferroelectric memory cell, comprising the steps of: writing a first polarization state in a ferroelectric capacitor of the memory cell by, a) applying a first polarizing voltage and polarity across.-the plates of the ferroelectric capacitor, b) isolating the ferroelectric capacitor plates so that a different voltage is trapped on each plate of the capacitor, and c) allowing the trapped voltages to reach a first equilibrium voltage during a first enhancement period to prolong an electric field in the ferroelectric material and enhance alignment of domains in a first direction in the ferroelectric material; writing a second polarization state in the ferroelectric capacitor of the memory cell by, d) applying a second polarizing voltage and polarity across the plates of the ferroelectric capacitor, e) isolating the ferroelectric capacitor plates so that a different voltage is trapped on each plate of the capacitor, and f) allowing the trapped voltages to reach a second equilibrium voltage different from the first equilibrium voltage during a second enhancement period to prolong an electric field in the ferroelectric material and enhance alignment of domains in a second direction in the ferroelectric material.

Claim 20

A method of enhancing polarization states in a ferroelectric memory cell, comprising the steps of: writing a first polarization state in a ferroelectric capacitor of the memory cell by, a) applying a first polarizing voltage and polarity across.-the plates of the ferroelectric capacitor, b) isolating the ferroelectric capacitor plates so that a different voltage is trapped on each plate of the capacitor, and c) allowing the trapped voltages to reach a first equilibrium voltage during a first enhancement period to prolong an electric field in the ferroelectric material and enhance alignment of domains in a first direction in the ferroelectric material; writing a second polarization state in the ferroelectric capacitor of the memory cell by, d) applying a second polarizing voltage and polarity across the plates of the ferroelectric capacitor, e) isolating the ferroelectric capacitor plates so that a different voltage is trapped on each plate of the capacitor, and f) allowing the trapped voltages to reach a second equilibrium voltage different from the first equilibrium voltage during a second enhancement period to prolong an electric field in the ferroelectric material and enhance alignment of domains in a second direction in the ferroelectric material.