US5175706A
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Programming voltage generator circuit for programmable memory
Assignee: STMicroelectronics SA
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Filing: 1991-05-23
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Granted: 1992-12-29
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Expires: 2011-05-23
Abstract
Abstract Electrically programmable memories often include an internal circuit for establishing a programming voltage Vpp higher than the supply voltage. This circuit is formed by a charge pump followed by a voltage regulator. Previously, an analog circuit was usually provided behind the regulator to convert the level of voltage Vpp, set up by the charge pump, into a signal with a slow-rising edge (to reduce the constraints on the programmed cells and increase their lifetime). Instead of such analog circuit, the present invention provides a digital control circuit to control the regulator to set up a regulation voltage that rises gradually from a low value up to the desired value Vpp. The digital control circuit comprises counter with k outputs which enables the gradual short-circuiting and unshort-circuiting of the various series-mounted transistors constituting the regulator, thus making the regulation voltage increase slowly.
Inventors
- 👤 Franck Edme
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:17
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/06; G11C16/10; G11C16/12; G11C16/30; G11C17/00; G11C17/14; G11C17/16; H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
111 words
An electrically programmable memory comprising a voltage generating circuit for establishing a programming voltage Vpp higher than a normal supply voltage of the memory, this voltage generating circuit including a voltage multiplier circuit delivering the voltage Vpp at its output and being followed by a voltage regulator to limit the voltage Vpp to a desired limit value, wherein there is provided a digital control means to digitally control the regulator in such a way as to achieve a gradual increase, by steps, in the limit voltage set up by the voltage regulator at the output of the voltage multiplier circuit, from a low value up to the desired value of Vpp.
Claim 2
Dependent Claim
111 words
An electrically programmable memory comprising a voltage generating circuit for establishing a programming voltage Vpp higher than a normal supply voltage of the memory, this voltage generating circuit including a voltage multiplier circuit delivering the voltage Vpp at its output and being followed by a voltage regulator to limit the voltage Vpp to a desired limit value, wherein there is provided a digital control means to digitally control the regulator in such a way as to achieve a gradual increase, by steps, in the limit voltage set up by the voltage regulator at the output of the voltage multiplier circuit, from a low value up to the desired value of Vpp.
Claim 3
Dependent Claim
108 words
An electrically programmable memory according to claim 1, wherein the regulator includes, between the voltage Vpp and the ground, a set of transistors in series, mounted as diodes with each transistor setting up a voltage, between its source and drain, that is equal to its threshold voltage, and wherein the digital control means includes a counter having a plurality of outputs and being capable of setting up a determined logic state successively at each of its outputs, and a means controlled by the outputs of the counter to initially short-circuit the transistors and then unshort-circuit them gradually one after the other as and when the counting takes place.
Claim 4
Dependent Claim
78 words
An electrically programmable memory according to claim 2, wherein the counter is a circuit with k outputs which, at each clock stroke, sets up a determined logic level on a new output of said counter, leaving in place, at each time, the level set up at the previous output of said counter, and wherein there is provision for a means to stop the counting when the last output of said counter has been placed at a determined level.
Claim 5
Dependent Claim
28 words
An electrically programmable memory according to claim 3, wherein the counter and the voltage multiplier circuit are activated by a signal that commands the programming of the memory.
Claim 6
Dependent Claim
44 words
An electrically programmable memory according to claim 4, wherein the digital control means increments the counter at a frequency of the order of k/2 to k kilohertz to obtain a rising time of the voltage Vpp of the order of 1 to 2 milliseconds.
Claim 7
Dependent Claim
24 words
An electrically programmable memory according to claim 4, wherein each of the transistors is made in a separate well diffused in a semiconductor substrate.
Claim 8
Dependent Claim
30 words
An electrically programmable memory according to claim 6, wherein the transistors are of the same type, and wherein the regulator includes at least one additional transistor of an opposite type.
Claim 9
Dependent Claim
54 words
An electrically programmable memory according to claim 2, wherein the counter includes k outputs and wherein the digital control means increments the outputs of the counter at a frequency of the order of k/2 to k kilohertz to obtain a rising time of the voltage Vpp of the order of 1 to 2 milliseconds.
Claim 10
Dependent Claim
24 words
An electrically programmable memory according to claim 2, wherein each of the transistors is made in a separate well diffused in a semiconductor substrate.
Claim 11
Dependent Claim
30 words
An electrically programmable memory according to claim 9, wherein the transistors are of the same type, and wherein the regulator includes at least one additional transistor of an opposite type.
Claim 12
Dependent Claim
47 words
An electrically programmable memory according to claim 3, wherein the digital control means increments the outputs of the counter at a frequency of the order of k/2 to k kilohertz to obtain a rising time of the voltage Vpp of the order of 1 to 2 milliseconds.
Claim 13
Dependent Claim
24 words
An electrically programmable memory according to claim 3, wherein each of the transistors is made in a separate well diffused in a semiconductor substrate.
Claim 14
Dependent Claim
30 words
An electrically programmable memory according to claim 12, wherein the transistors are of the same type, and wherein the regulator includes at least one additional transistor of an opposite type.
Claim 15
Dependent Claim
51 words
An electrically programmable memory according to claim 1, wherein the digital control means includes k outputs and a circuit for incrementing the outputs at a frequency of the order of k/2 to k kilohertz to obtain a rising time of the voltage Vpp of the order of 1 to 2 milliseconds.
Claim 16
Dependent Claim
98 words
A voltage generating circuit for establishing a voltage Vpp higher than a normal supply voltage, comprising a voltage multiplier circuit delivering the voltage Vpp at its output and being followed by a voltage regulator to limit the voltage Vpp to a desired limit value, wherein there is provided a digital control circuit to digitally control the regulator in such a way as to achieve a gradual increase, by steps, in the limit voltage set up by the voltage regulator at the output of the voltage multiplier circuit, from a low value up to the desired value of Vpp.
Claim 17
Dependent Claim
98 words
A voltage generating circuit for establishing a voltage Vpp higher than a normal supply voltage, comprising a voltage multiplier circuit delivering the voltage Vpp at its output and being followed by a voltage regulator to limit the voltage Vpp to a desired limit value, wherein there is provided a digital control circuit to digitally control the regulator in such a way as to achieve a gradual increase, by steps, in the limit voltage set up by the voltage regulator at the output of the voltage multiplier circuit, from a low value up to the desired value of Vpp.
Claim 18
Dependent Claim
124 words
A voltage generating circuit according to claim 15, wherein the regulator includes, between the voltage Vpp and the ground, a set of transistors in series, mounted as diodes with each transistor setting up a voltage, between its source and drain, that is equal to its threshold voltage, and wherein the digital control circuit includes a counter having a plurality of outputs and being capable of setting up a determined logic state successively at each of its outputs, a clock for providing clock pulses to said counter, and a circuit controlled by the outputs of the counter to initially short-circuit the transistors and then unshort-circuit them gradually one after the other as and when the counting of the clock pulses by the counter takes place.
Claim 19
Dependent Claim
54 words
A voltage generating circuit according to claim 16, wherein the counter includes k outputs and wherein the digital control circuit increments the outputs of the counter at a frequency of the order of k/2 to k kilohertz to obtain a rising time of the voltage Vpp of the order of 1 to 2 milliseconds.
Claim 20
Dependent Claim
24 words
A voltage generating circuit according to claim 16, wherein each of the transistors is made in a separate well diffused in a semiconductor substrate.
Claim 21
Dependent Claim
30 words
A voltage generating circuit according to claim 18, wherein the transistors are of the same type, and wherein the regulator includes at least one additional transistor of an opposite type.
Claim 22
Dependent Claim
81 words
A voltage generating circuit according to claim 16, wherein the counter is a circuit with k outputs which, at each clock pulse inputted thereto, sets up a determined logic level on a new output of said counter, leaving in place, at each time, the level set up at the previous output of said counter; and further comprising a circuit to stop the counting of the clock pulses when the last output of said counter has been placed at a determined level.
Claim 23
Dependent Claim
47 words
A voltage generating circuit according to claim 20, wherein the digital control circuit increments the outputs of the counter at a frequency of the order of k/2 to k kilohertz to obtain a rising time of the voltage Vpp of the order of 1 to 2 milliseconds.
Claim 24
Dependent Claim
24 words
A voltage generating circuit according to claim 20, wherein each of the transistors is made in a separate well diffused in a semiconductor substrate.
Claim 25
Dependent Claim
30 words
A voltage generating circuit according to claim 22, wherein the transistors are of the same type, and wherein the regulator includes at least one additional transistor of an opposite type.
Claim 26
Dependent Claim
43 words
An electrically programmable memory comprising a voltage generating circuit according to claim 20 for establishing the programming voltage Vpp for the memory, and wherein the counter and the voltage multiplier circuit are activated by a signal that commands the programming of the memory.
Claim 27
Dependent Claim
51 words
An electrically programmable memory according to claim 24, wherein the digital control circuit includes k outputs and a circuit for incrementing the outputs at a frequency of the order of k/2 to k kilohertz to obtain a rising time of the voltage Vpp of the order of 1 to 2 milliseconds.
Claim 28
Dependent Claim
24 words
An electrically programmable memory according to claim 24, wherein each of the transistors is made in a separate well diffused in a semiconductor substrate.
Claim 29
Dependent Claim
30 words
An electrically programmable memory according to claim 24, wherein the transistors are of the same type, and wherein the regulator includes at least one additional transistor of an opposite type.
Claim 30
Dependent Claim
51 words
A voltage generating circuit according to claim 15, wherein the digital control circuit includes k outputs and a circuit for incrementing the outputs at a frequency of the order of k/2 to k kilohertz to obtain a rising time of the voltage Vpp of the order of 1 to 2 milliseconds.
References Cited (Backward Citations)
US4447747A
Cited
EP0217718A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-29 | 1996-06-29 | 1996-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-29 | 2000-06-29 | 2000-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-29 | 2004-06-29 | 2004-12-29 | $7700.00 | Window Closed / Lapsed |