EP0217718A2
Expired / Lapsed
EP
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Nonvolatile memory circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1986-10-03
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Granted: —
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Expires: 2006-10-03
Abstract
Abstract An improved nonvolatile memory has an adaptive system to regulate the charging current supplied to store data on nonvolatile storage nodes in order to provide acceptability low strain on the tunnel oxide and to compensate for process variations and change in the Fowler-Nordheim tunnel oxide transport characteristics caused by electron trapping over time.
Inventors
- 👤 Horst Leuschner
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 04:16
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C14/00; G11C16/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
158 words
A nonvolatile memory circuit comprising an array of nonvolatile memory elements; means for applying data to said array of nonvolatile memory elements; and means for applying high voltage to selected terminals of said nonvolatile memory elements, thereby storing said data applied to said array of nonvolatile memory elements; characterized in that: said means for applying high voltage comprises at least one dual node floating gate nonvolatile memory cell having first and second floating gates and a maximum voltage terminal and a minimum voltage terminal, said terminals carrying the maximum and minimum voltage of those voltages on said first and second floating gates of said at least one dual node memory cell; comparison means for comparing said maximum and minimum voltages; and means for terminating the application of high voltage to said selected terminals in response to a signal from said comparison means indicating a voltage difference between said maximum and minimum voltages less then a predetermined cutoff value.
Claim 2
Dependent Claim
158 words
A nonvolatile memory circuit comprising an array of nonvolatile memory elements; means for applying data to said array of nonvolatile memory elements; and means for applying high voltage to selected terminals of said nonvolatile memory elements, thereby storing said data applied to said array of nonvolatile memory elements; characterized in that: said means for applying high voltage comprises at least one dual node floating gate nonvolatile memory cell having first and second floating gates and a maximum voltage terminal and a minimum voltage terminal, said terminals carrying the maximum and minimum voltage of those voltages on said first and second floating gates of said at least one dual node memory cell; comparison means for comparing said maximum and minimum voltages; and means for terminating the application of high voltage to said selected terminals in response to a signal from said comparison means indicating a voltage difference between said maximum and minimum voltages less then a predetermined cutoff value.
Claim 3
Dependent Claim
63 words
A nonvolatile memory circuit according to Claim 1, further characterized in that: said means for applying high voltage further comprises charge pump means, controlled by said comparison means, for generating current from a charge pump output terminal at said high voltage and current regulator means connected to said charge pump output terminal for limiting the magnitude of current flowing from said charge pump.
Claim 4
Dependent Claim
77 words
A nonvolatile memory circuit according to Claim 1, further characterized in that: said circuit comprises at least one dual node floating gate nonvolatile reference memory element connected to said comparison means; and at least one nonvolatile data memory element connected to a data terminal for storing data on said data terminal by application of high voltage to a selected terminal of said nonvolatile data memory element, said high voltage being under control of said reference memory element.
Claim 5
Dependent Claim
66 words
A nonvolatile memory circuit according to Claim 1, further characterized in that: all of said array of nonvolatile memory elements comprise dual node floating gate memory cells, each having said maximum and minimum voltage terminals, at least two sets of said maximum and minimum voltage terminals are interconnected to provide the highest maximum voltage and the lowest minimum voltage of said maximum and minimum voltage terminals.
References Cited (Backward Citations)
No citation records indexed.
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