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Patent US5309168A successfully refreshed from Google Patents.
US5309168A
Expired / Lapsed
US
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Panel display control device
Assignee: Yamaha Corp
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Filing: 1991-10-30
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Granted: 1994-05-03
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Expires: 2011-10-30
Abstract
Abstract A CRT controller is operated in accordance with a basic clock for a panel display and repeats a wait operation in response to a wait signal produced by a panel timing controller, which causes a compulsory synchronization with the panel timing. A 1/2 frame buffer is also provided. Display data supplied by the CRT controller and display data read from the 1/2 frame buffer are alternately selected such that data is supplied in an order conforming to the panel display of a double screen type panel display. A display of the double screen type panel display is controlled in accordance with an application program directed to a CRT display without modifying the order of the display data produced by the CRT controller and without changing the timing data which has been set in the CRT controller. The 1/2 frame buffer may be a general-purpose memory which stores 1/2 frame and one line of the panel display data. A 1/2 frame buffer control circuit shifts a writing address of the 1/2 frame buffer by one line in a reverse direction to a direction of scanning for writing at the beginning of each new frame.
Inventors
- 👤 Shuhei Itoh
- 👤 Mitsuhiro Kurata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:02
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3622; G09G3/3644
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
283 words
A panel display control device for use with display data, the device comprising: a clock for providing a basic clock; a panel display having a first screen and a second screen display; a CRT controller operated in response to the basic clock and a stored set of values for a CRT timing to provide a display timing signal for the panel display and display data in accordance with the set value of the CRT timing; a panel data conversion circuit for converting the display data provided by the CRT controller to panel display data for the panel display; a buffer for storing at least 1/2 frame of the panel display data provided by the panel data conversion circuit; a panel timing controller operated in response to the basic clock and providing a wait signal for synchronizing the CRT controller with the panel display timing without changing the stored set of values for the CRT timing, the panel timing controller further providing a screen switching signal for switching the first and second screens synchronized with the wait signal, and a display control signal for the panel display; a buffer control circuit for controlling a read timing and a write timing of the buffer in response to the screen switching signal, such that the panel display data provided by the panel data conversion circuit is written line by line into the buffer and is read out from the buffer line by line; and a data control circuit for alternately selecting line by line between the panel display data provided by the panel data conversion circuit and panel display data provided by the buffer, such that the selected display data is supplied to the panel display.
Claim 2
Dependent Claim
283 words
A panel display control device for use with display data, the device comprising: a clock for providing a basic clock; a panel display having a first screen and a second screen display; a CRT controller operated in response to the basic clock and a stored set of values for a CRT timing to provide a display timing signal for the panel display and display data in accordance with the set value of the CRT timing; a panel data conversion circuit for converting the display data provided by the CRT controller to panel display data for the panel display; a buffer for storing at least 1/2 frame of the panel display data provided by the panel data conversion circuit; a panel timing controller operated in response to the basic clock and providing a wait signal for synchronizing the CRT controller with the panel display timing without changing the stored set of values for the CRT timing, the panel timing controller further providing a screen switching signal for switching the first and second screens synchronized with the wait signal, and a display control signal for the panel display; a buffer control circuit for controlling a read timing and a write timing of the buffer in response to the screen switching signal, such that the panel display data provided by the panel data conversion circuit is written line by line into the buffer and is read out from the buffer line by line; and a data control circuit for alternately selecting line by line between the panel display data provided by the panel data conversion circuit and panel display data provided by the buffer, such that the selected display data is supplied to the panel display.
Claim 3
Dependent Claim
62 words
A panel display control device as defined in claim 1, wherein the buffer comprises a general-purpose memory for storing 1/2 frame and one line of the panel display data, and wherein the buffer control circuit shifts a writing start address of the buffer by one line a reverse direction to a scanning direction for writing at a beginning of each new frame.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-02 | 1997-11-01 | 1998-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-02 | 2001-11-01 | 2002-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-02 | 2005-11-01 | 2006-05-03 | $7700.00 | Window Closed / Lapsed |