Network adapter with host indication optimization

Claim 3

The apparatus of claim 1, wherein the network interface logic includes: receive logic for transferring a received data frame from the network transceiver to the buffer memory.

Claim 4

The apparatus of claim 1, wherein the host interface logic includes: transfer descriptor logic for mapping transfer descriptors from the host system to the buffer memory, the transfer descriptors identifying locations in host memory to which a data frame in the buffer memory is to be stored; and upload logic, responsive to transfer descriptors in the buffer memory, for transferring a data frame from the buffer memory to host memory.

Claim 5

The apparatus of claim 1, wherein the host interface logic includes: transmit descriptor logic for mapping transmit descriptors identifying a data frame to be transmitted from the host memory to the buffer memory; and download logic, responsive to transmit descriptors in the buffer memory, for retrieving a data frame from host memory and storing a retrieved data frame in the buffer memory; and wherein the network interface logic includes: transmit logic responsive to transmit descriptors in the buffer memory for retrieving a data frame from the buffer memory and supplying a retrieved data frame to the network transceiver for transmission on the network.

Claim 6

The apparatus of claim 1, wherein the network interface logic includes: control means for generating an interrupt signal to the host processor responsive to the indication signal and posting status information which may be used by the host processor as feedback for optimizing the threshold value.

Claim 7

The apparatus of claim 1, wherein the buffer memory comprises a buffer independent of the host address space.

Claim 8

The apparatus of claim 1, wherein the data frame includes a header field followed by a data field.

Claim 9

The apparatus of claim 7, wherein the threshold value is a look-ahead threshold value representing an amount of data relative to the beginning of the header field.

Claim 10

The apparatus of claim 8, wherein the look-ahead threshold value is greater than the amount of data used for the header field.

Claim 11

The apparatus of claim 9, wherein the threshold value represents an amount of data such that a successful reception of the data frame is likely after receiving the threshold value of data.

Claim 12

An apparatus of claim 1, further comprising: view logic for presenting the data frame in the buffer memory to the host system prior to transferring to the host memory, in response to host system access to a prespecified portion of host memory.

Claim 13

An apparatus of claim 1, wherein the indication signal includes an early receive signal.

Claim 14

An apparatus of claim 1, wherein the indication signal includes a receive complete signal.

Claim 15

The apparatus of claim 7, further comprising: error detection means, for checking the data field transferred from the network transceiver to the buffer memory and generating a receive frame status signal.

Claim 16

The apparatus of claim 7, wherein the threshold value is a length-left threshold value representing an amount of data relative to the end of the data field.

Claim 17

The apparatus of claim 1, wherein the threshold value is a transfer complete threshold value representing an amount of data transferred to the host memory from the buffer memory.

Claim 18

The apparatus of claim 16, wherein the indication signal includes a transfer complete signal.

Claim 19

The apparatus of claim 1, wherein the threshold value is a download complete threshold value representing an amount of data transferred to the buffer memory from the host memory.

Claim 20

The apparatus of claim 18, wherein the indication signal includes a download complete signal.

Claim 21

The apparatus of claim 1, wherein the threshold value is a transmit complete threshold value representing an amount of data transferred from the buffer memory to the network transceiver.

Claim 22

The apparatus of claim 20, wherein the indication signal includes a transmit complete signal.

Claim 23

A network adapter for receiving a data frame from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; receive threshold logic for generating an indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a receive threshold value; means for comparing the counter to the receive threshold value in the alterable storage location and generating an indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the indication signal, which reduces host processor interrupt latency.

Claim 24

A network adapter for receiving a data frame from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; receive threshold logic for generating an indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a receive threshold value; means for comparing the counter to the receive threshold value in the alterable storage location and generating an indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the indication signal, which reduces host processor interrupt latency.

Claim 25

The network adapter of claim 22, wherein control means includes: means for posting status information, responsive to the indication signal, which may be used by the host processor in binary exponential acceleration tracking for optimizing the threshold value.

Claim 26

The network adapter of claim 22, wherein the host interface logic further includes: transfer descriptor logic for mapping transfer descriptors from the host system to the buffer memory, the transfer descriptors identifying locations in host memory to which a data frame in the buffer memory is to be stored; and upload logic, responsive to transfer descriptors in the buffer memory, for transferring a data frame from the buffer memory to host memory.

Claim 27

The network adapter of claim 22, wherein the buffer memory comprises a buffer independent of the host address space.

Claim 28

The network adapter of claim 22, wherein the data frame includes a header field followed by a data field.

Claim 29

The network adapter of claim 26, wherein the receive threshold value is a look-ahead threshold value representing an amount of data relative to the beginning of the header field.

Claim 30

The network adapter of claim 27, wherein the look-ahead threshold value is greater than the amount of data used for the header field.

Claim 31

The network adapter of claim 26, wherein the receive threshold value represents an amount of data such that a successful reception of the data frame is likely after receiving the threshold value of data.

Claim 32

A network adapter of claim 22, further comprising: view logic for presenting the data frame in the buffer memory to the host system prior to transferring to the host memory, in response to host system access to a prespecified portion of host memory.

Claim 33

A network adapter of claim 22, wherein the indication signal includes an early receive signal.

Claim 34

The network adapter of claim 26, further comprising: error detection means, for checking the data field transferred from the network transceiver to the buffer memory and generating a receive frame status signal.

Claim 35

The network adapter of claim 26, wherein the receive threshold value is a length-left threshold value representing an amount of data relative to the end of the data field.

Claim 36

A network adapter for receiving a data frame which includes a header field followed by a data field from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; look-ahead threshold logic for generating an early receive indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a look-ahead threshold value representing an amount of data relative to the beginning of the header field; means for comparing the counter to the look-ahead threshold value in the alterable storage location and generating an early receive indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early receive indication signal, which reduces host processor interrupt latency.

Claim 37

A network adapter for receiving a data frame which includes a header field followed by a data field from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; look-ahead threshold logic for generating an early receive indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a look-ahead threshold value representing an amount of data relative to the beginning of the header field; means for comparing the counter to the look-ahead threshold value in the alterable storage location and generating an early receive indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early receive indication signal, which reduces host processor interrupt latency.

Claim 38

The network adapter of claim 34, wherein control means includes: means for posting status information, responsive to the early receive indication signal, which may be used by the host processor in binary exponential acceleration tracking for optimizing the look-ahead threshold value.

Claim 39

The network adapter of claim 34, wherein the look-ahead threshold value is greater than the amount of data used for the header field.

Claim 40

The network adapter of claim 34, wherein the look-ahead threshold value represents an amount of data such that a successful reception of the data frame is likely after receiving the look-ahead threshold value of data.

Claim 41

An network adapter of claim 34, further comprising: view logic for presenting the data frame in the buffer memory to the host system prior to transferring to the host memory, in response to host system access to a prespecified portion of host memory.

Claim 42

The network adapter of claim 34, further comprising: error detection means, for checking the data field transferred from the network transceiver to the buffer memory and generating a receive frame status signal, which may be used by the host processor.

Claim 43

A network adapter for receiving a data frame which includes a header field followed by a data field from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; length-left threshold logic for generating a receive complete indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a length-left threshold value representing an amount of data relative to the end of the data field; means for comparing the counter to the length-left threshold value in the alterable storage location and generating a receive complete indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the receive complete indication signal, which reduces host processor interrupt latency.

Claim 44

A network adapter for receiving a data frame which includes a header field followed by a data field from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; receive logic for receiving the data frame from the network transceiver to the buffer memory; length-left threshold logic for generating a receive complete indication signal during the receiving of the data frame, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data received by the buffer memory; an alterable storage location containing a length-left threshold value representing an amount of data relative to the end of the data field; means for comparing the counter to the length-left threshold value in the alterable storage location and generating a receive complete indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the receive complete indication signal, which reduces host processor interrupt latency.

Claim 45

The network adapter of claim 40, wherein control means includes: means for posting status information, responsive to the receive complete indication signal, which may be used by the host processor in binary exponential acceleration tracking for optimizing the length-left threshold value.

Claim 46

An network adapter of claim 40, further comprising: view logic for presenting the data frame in the buffer memory to the host system prior to transferring to the host memory, in response to host system access to a prespecified portion of host memory.

Claim 47

The network adapter of claim 40, further comprising: error detection means, for checking the data field transferred from the network transceiver to the buffer memory and generating a receive frame status signal.

Claim 48

A network adapter for transferring a data frame from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame, which includes a data field; receive logic for receiving the data frame from the network transceiver to the buffer memory; transfer threshold logic for generating an early transfer indication signal during the transferring of the data frame from the buffer memory to the host system, wherein the transfer threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transferred from the buffer memory; an alterable storage location containing a transfer threshold value; means for comparing the counter to the transfer threshold value in the alterable storage location and generating an early transfer indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early transfer indication signal, which reduces host processor interrupt latency.

Claim 49

A network adapter for transferring a data frame from a network transceiver, coupled with a network and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame, which includes a data field; receive logic for receiving the data frame from the network transceiver to the buffer memory; transfer threshold logic for generating an early transfer indication signal during the transferring of the data frame from the buffer memory to the host system, wherein the transfer threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transferred from the buffer memory; an alterable storage location containing a transfer threshold value; means for comparing the counter to the transfer threshold value in the alterable storage location and generating an early transfer indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the buffer memory to the host system, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early transfer indication signal, which reduces host processor interrupt latency.

Claim 50

The network adapter of claim 44, wherein control means includes: means for posting status information, responsive to the early transfer indication signal, which may be used by the host processor in binary exponential acceleration tracking for optimizing the transfer threshold value.

Claim 51

The network adapter of claim 44, wherein the host interface logic further includes: transfer descriptor logic for mapping transfer descriptors from the host system to the buffer memory, the transfer descriptors identifying locations in host memory to which a data frame in the buffer memory is to be stored; and upload logic, responsive to transfer descriptors in the buffer memory, for transferring a data frame from the buffer memory to host memory.

Claim 52

The network adapter of claim 44, wherein the buffer memory comprises a buffer independent of the host address space.

Claim 53

An network adapter of claim 44, further comprising: view logic for presenting the data frame in the buffer memory to the host system prior to transferring to the host memory, in response to host system access to a prespecified portion of host memory.

Claim 54

The network adapter of claim 44, further comprising: error detection means, for checking the data field transferred from the network transceiver to the buffer memory and generating a receive frame status signal.

Claim 55

A network adapter for transmitting a data frame across a communication medium, the network adapter coupled to the communicating medium and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; communication interface logic for transmitting the data frame across the communication media from the buffer memory; transmit threshold logic for generating an early transmit indication signal during the transmitting of the data frame, wherein the transmit threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transmitted from the buffer memory; an alterable storage location containing a transmit threshold value, representing the amount of data to be transmitted across the communication media; means for comparing the counter to the transmit threshold value in the alterable storage location and generating a transmit complete indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the host system to the buffer memory, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early transmit indication signal, which reduces host processor interrupt latency.

Claim 56

A network adapter for transmitting a data frame across a communication medium, the network adapter coupled to the communicating medium and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; communication interface logic for transmitting the data frame across the communication media from the buffer memory; transmit threshold logic for generating an early transmit indication signal during the transmitting of the data frame, wherein the transmit threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transmitted from the buffer memory; an alterable storage location containing a transmit threshold value, representing the amount of data to be transmitted across the communication media; means for comparing the counter to the transmit threshold value in the alterable storage location and generating a transmit complete indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the host system to the buffer memory, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early transmit indication signal, which reduces host processor interrupt latency.

Claim 57

The network adapter of claim 50, wherein control means includes: means for posting status information, responsive to the indication signal, which may be used by the host processor in binary exponential acceleration tracking for optimizing the transmit threshold value.

Claim 58

A network adapter for transmitting a data frame across a communication medium, the network adapter coupled to the communication medium and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; communication interface logic for transmitting the data frame across the communication medium from the buffer memory; download transmit threshold logic for generating an early download transmit indication signal during the transferring of the data frame from the host system to the buffer memory, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transferred to the buffer memory; an alterable storage location containing a download transmit threshold value representing the amount of data transferred to the buffer memory for transmitting across the communication media; means for comparing the counter to the download transmit threshold value in the alterable storage location and generating an indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the host system to the buffer memory, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early download transmit indication signal, which reduces host processor interrupt latency.

Claim 59

A network adapter for transmitting a data frame across a communication medium, the network adapter coupled to the communication medium and a host system which includes an interruptable host processor with interrupt latency and host memory, comprising: a buffer memory for storing the data frame; communication interface logic for transmitting the data frame across the communication medium from the buffer memory; download transmit threshold logic for generating an early download transmit indication signal during the transferring of the data frame from the host system to the buffer memory, wherein the receive threshold logic includes, a counter, coupled to the buffer memory, for counting the amount of data transferred to the buffer memory; an alterable storage location containing a download transmit threshold value representing the amount of data transferred to the buffer memory for transmitting across the communication media; means for comparing the counter to the download transmit threshold value in the alterable storage location and generating an indication signal responsive to a comparison of the counter and the alterable storage location; and host interface logic for transferring the data frame from the host system to the buffer memory, wherein host interface logic includes, control means for generating an interrupt signal to the host processor, responsive to the early download transmit indication signal, which reduces host processor interrupt latency.

Claim 60

The network adapter of claim 52, wherein control means includes: means for posting status information, responsive to the indication signal, which may be used by the host processor in binary exponential acceleration tracking for optimizing the download transmit threshold value.