US5307355A
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Method and apparatus for generating a 48-bit frame check sequence
Assignee: Enterasys Networks Inc
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Filing: 1991-01-30
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Granted: 1994-04-26
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Expires: 2011-01-30
Abstract
Abstract A node operating in a network using the International Standard Organization (ISO) High-Level Data Link Control (HDLC) network protocol includes a mechanism for encoding information such that frames including the encoded information can be correctly interpreted by nodes operating in either of the standard 16-bit or 32-bit ISO-HDLC operating modes. The encoding mechanism produces a preliminary frame check sequence by encoding the information in an encoder using a generator polynomial G 48 (x), which is a combination of the generator polynomials G 16 (x) and G 32 (x) which are used to produce frame check sequences for nodes operating in 16-bit or 32-bit modes, respectively. Before the information is encoded, the encoding mechanism sets the encoder to an initial condition using an initializing polynomial I 48 (x). The preliminary frame check sequence is further encoded by adding to it a complementing polynomial C 48 (x). The result is a 48-bit frame check sequence. The encoding mechanism appends the 48-bit frame check sequence to the information, and transmits the information and the appended 48-bit frame check sequence over the network as part of a frame.
Inventors
- 👤 Anthony G. Lauck
- 👤 Ian M. C. Shand
- 👤 John Harper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:31
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0061; H04L1/0057
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
146 words
A system for transmitting digital messages comprising: a transmitter encoder unit operating with a predetermined bit-length of 48 bits effective to produce a frame check sequence from a message and to append the frame check sequence to the message, the message and its appended frame check sequence being capable of being checked by a receiver encoder unit operating in a first mode having a shorter bit-length of 16 bits and by a receiver encoder unit operating in a second mode having a bit-length of 32 bits; a line driver for transmitting the message and its appended frame check sequence over a communication link; a line receiver for receiving the message and its appended frame check sequence from the communication link; and a receiver encoder unit for checking the message and its appended frame check sequence, the receiver encoder unit operating in one of the two modes.
Claim 2
Independent Claim
146 words
A system for transmitting digital messages comprising: a transmitter encoder unit operating with a predetermined bit-length of 48 bits effective to produce a frame check sequence from a message and to append the frame check sequence to the message, the message and its appended frame check sequence being capable of being checked by a receiver encoder unit operating in a first mode having a shorter bit-length of 16 bits and by a receiver encoder unit operating in a second mode having a bit-length of 32 bits; a line driver for transmitting the message and its appended frame check sequence over a communication link; a line receiver for receiving the message and its appended frame check sequence from the communication link; and a receiver encoder unit for checking the message and its appended frame check sequence, the receiver encoder unit operating in one of the two modes.
Claim 3
Dependent Claim
32 words
The system of claim 1 wherein the frame check sequence is a 48-bit frame check sequence and the first mode is a 16-bit mode and the second mode is a 32-bit mode.
Claim 4
Dependent Claim
48 words
The system of claim 2 wherein the transmitter encoder unit comprises: an encoder for encoding the message with a generator polynomial; means for initializing the encoder with an initialization polynomial; and means for adding a complementing polynomial to the encoded message effective to produce the frame check sequence.
Claim 5
Dependent Claim
207 words
The system of claim 3 wherein: the generator polynomial is the product of the 16-bit and the 32-bit standard generator polynomials specified by the International Standard Organization (ISO) High-level Data Link Control (HDLC) protocol; the initialization polynomial equals x 47 + x 46 + x 43 + x 42 + x 39 + x 37 + x 34 + x 32 + x 31 + x 30 + x 29 + x 27 + x 25 + x 23 + x 22 + x 21 + x 20 + x 19 + x 17 + x 16 + x 15 + x 11 + x 10 + x 9 + x 8 + x 5 + x 4 + x 2 + x+ 1; and the complementing polynomial equals x 45 + x 44 + x 41 + x 40 + x 38 + x 36 + x 35 + x 33 + x 31 + x 30 + x 29 + x 27 + x 25 + x 23 + x 22 + x 21 + x 20 + x 19 + x 17 + x 16 + x 14 + x 13 + x 12 + x 7 + x 6 + x 3 .
Claim 6
Dependent Claim
25 words
The system of claim 4 wherein the receiver encoder unit is effective to operate in accordance with the 32-bit mode of the ISO HDLC protocol.
Claim 7
Dependent Claim
25 words
The system of claim 4 wherein the receiver encoder unit is effective to operate in accordance with the 16-bit mode of the ISO HDLC protocol.
Claim 8
Dependent Claim
183 words
A network node for transmitting digital messages comprising: means for generating a 48-bit frame check sequence from a message, the message and its appended 48-bit frame check sequence being capable of being checked by a 16-bit receiver encoder unit and by a 32-bit receiver encoder unit; means for appending the high order 16 bits of the 48-bit frame check sequence to the message; a transmitter encoder unit effective to operate in accordance with the 32-bit mode of the International Standard Organization (ISO) High-level Data Link Control (HDLC) protocol, the transmitter encoder unit further effective to receive the message and its 16-bit frame check sequence segment and to generate, using standard 32-bit ISO generator codes, a 32-bit frame check sequence therefrom; means for appending the 32-bit frame check sequence to the 16-bit frame check sequence segment, the combination of the 16-bit frame check sequence segment and appended 32-bit frame check sequence being equal to the 48-bit frame check sequence; and a line driver for transmitting the message, its 16-bit frame check sequence segment, and the appended 32-bit frame check sequence over a communication link.
Claim 9
Dependent Claim
183 words
A network node for transmitting digital messages comprising: means for generating a 48-bit frame check sequence from a message, the message and its appended 48-bit frame check sequence being capable of being checked by a 16-bit receiver encoder unit and by a 32-bit receiver encoder unit; means for appending the high order 16 bits of the 48-bit frame check sequence to the message; a transmitter encoder unit effective to operate in accordance with the 32-bit mode of the International Standard Organization (ISO) High-level Data Link Control (HDLC) protocol, the transmitter encoder unit further effective to receive the message and its 16-bit frame check sequence segment and to generate, using standard 32-bit ISO generator codes, a 32-bit frame check sequence therefrom; means for appending the 32-bit frame check sequence to the 16-bit frame check sequence segment, the combination of the 16-bit frame check sequence segment and appended 32-bit frame check sequence being equal to the 48-bit frame check sequence; and a line driver for transmitting the message, its 16-bit frame check sequence segment, and the appended 32-bit frame check sequence over a communication link.
Claim 10
Dependent Claim
57 words
The network node of claim 7 wherein the means for generating a 48-bit frame check sequence comprises: means for encoding the message with a generator polynomial; and means for initializing the means for encoding with an initialization polynomial; and means for adding a complementing polynomial to the encoded message effective to produce the 48-bit frame check sequence.
Claim 11
Dependent Claim
191 words
The network node of claim 8 wherein: the generator polynomial is the product of the 16-bit and the 32-bit standard generator polynomials specified by the ISO HDLC protocol; the initialization polynomial equals x 47 + x 46 + x 43 + x 42 + x 39 + x 37 + x 34 + x 32 + x 31 + x 30 + x 29 + x 27 + x 25 + x 23 + x 22 + x 21 + x 20 + x 19 + x 17 + x 16 + x 15 + x 11 + x 10 + x 9 + x 8 + x 5 + x 4 + x 2 + x+ 1; and the complementary polynomial equals x 45 + x 44 + x 41 + x 40 +x 38 +x 36 +x 35 +x 33 +x 31 +x 30 +x 29 +x 27 +x 25 +x 23 + x 22 + x 21 + x 20 + x 19 + x 17 + x 16 + x 14 + x 13 + x 12 + x 7 + x 6 + x 3 .
Claim 12
Dependent Claim
20 words
The network node of claim 9 wherein the means for generating a 48-bit frame check sequence is embodied in software.
Claim 13
Dependent Claim
183 words
A network node for transmitting digital messages comprising: means for generating a 48-bit frame check sequence from a message, the message and its appended 48-bit frame check sequence being capable of being checked by a 16-bit receiver encoder unit and by a 32-bit receiver encoder unit; means for appending the high order 32 bits of the 48-bit frame check sequence to the message; a transmitter encoder unit effective to operate in accordance with the 16-bit mode of the International Standard Organization (ISO) High-level Data Link Control (HDLC) protocol, the transmitter encoder unit further effective to receive the message and its 32-bit frame check sequence segment and to generate, using standard 16-bit ISO generator codes, a 16-bit frame check sequence therefrom; means for appending the 16-bit frame check sequence to the 32-bit frame check sequence segment, the combination of the 32-bit frame check sequence segment and appended 16-bit frame check sequence being equal to the 48-bit frame check sequence; and a line driver for transmitting the message, its 32-bit frame check sequence segment, and the appended 16-bit frame check sequence over a communication link.
Claim 14
Dependent Claim
183 words
A network node for transmitting digital messages comprising: means for generating a 48-bit frame check sequence from a message, the message and its appended 48-bit frame check sequence being capable of being checked by a 16-bit receiver encoder unit and by a 32-bit receiver encoder unit; means for appending the high order 32 bits of the 48-bit frame check sequence to the message; a transmitter encoder unit effective to operate in accordance with the 16-bit mode of the International Standard Organization (ISO) High-level Data Link Control (HDLC) protocol, the transmitter encoder unit further effective to receive the message and its 32-bit frame check sequence segment and to generate, using standard 16-bit ISO generator codes, a 16-bit frame check sequence therefrom; means for appending the 16-bit frame check sequence to the 32-bit frame check sequence segment, the combination of the 32-bit frame check sequence segment and appended 16-bit frame check sequence being equal to the 48-bit frame check sequence; and a line driver for transmitting the message, its 32-bit frame check sequence segment, and the appended 16-bit frame check sequence over a communication link.
Claim 15
Dependent Claim
57 words
The network node of claim 11 wherein the means for generating a 48-bit frame check sequence comprises: means for encoding the message with a generator polynomial; and means for initializing the means for encoding with an initialization polynomial; and means for adding a complementing polynomial to the encoded message effective to produce the 48-bit frame check sequence.
Claim 16
Dependent Claim
201 words
The network node of claim 12 wherein: the generator polynomial is the product of the 16-bit and the 32-bit standard generator polynomials specified by the ISO HDLC protocol; the initialization polynomial equals x 47 + x 46 + x 43 + x 42 + x 39 + x 37 + x 34 + x 32 + x 31 + x 30 + x 29 + x 27 + x 25 + x 23 + x 22 + x 21 + x 20 + x 19 + x 17 + x 16 + x 15 + x 11 + x 10 + x 9 + x 8 + x 5 + x 4 + x 2 + x+ 1; and the complementing polynomial equals x 45 + x 44 + x 41 + x 40 + x 38 + x 36 + x 35 + x 33 + x 31 + x 30 + x 29 + x 27 + x 25 + x 23 + x 22 + x 21 + x 20 + x 19 + x 17 + x 16 + x 14 + x 13 + x 12 + x 7 + x 6 + x 3 .
Claim 17
Dependent Claim
20 words
The network node of claim 13 wherein the means for generating a 48-bit frame check sequence is embodied in software.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-25 | 1997-10-25 | 1998-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-25 | 2001-10-25 | 2002-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-25 | 2005-10-25 | 2006-04-26 | $7700.00 | Window Closed / Lapsed |