EP0225761A2
Expired / Lapsed
EP
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Apparatus and method for calculating cyclical redundancy codes
Assignee: Advanced Micro Devices Inc
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Filing: 1986-11-24
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Granted: —
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Expires: 2006-11-24
Abstract
Abstract There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the input of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock. Preset logic for forcing all logic 1 's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several different architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC for the header. Logic for allowing CRC calculation to be performed on all bytes of a message while excluding some selected number of bits in the first byte is also disclosed.
Inventors
- 👤 Sunil P. Joshi
- 👤 Venkatraman Iyer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 09:58
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; H03M13/091
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
193 words
An apparatus for calculating CRC bits on a data packet comprised of a plurality of bytes of data where one or more bits in the first byte may be excluded from the CRC calculation comprising: a CRC checksum register comprised of a plurality of memory cells each having a data input, a data output and a byte clock input for receiving a byte clock signal causing loading of data at said data input into said memory cells; a calculation means having a data outputs coupled to said data inputs of said CRC checksum register and having data inputs coupled to said data outputs of said CRC checksum register and having a raw data input, said calculation means for accepting input data from said CRC checksum register and raw input data bytes at said raw data input and for dividing said raw input data by a predetermined bit pattern and for storing the remainder of said division in said CRC checksum register as said CRC check bits; and ignoring means coupled to said calculation means for causing said calculation means to ignore designated bits in said raw input data while performing said CRC calculation.
Claim 2
Independent Claim
193 words
An apparatus for calculating CRC bits on a data packet comprised of a plurality of bytes of data where one or more bits in the first byte may be excluded from the CRC calculation comprising: a CRC checksum register comprised of a plurality of memory cells each having a data input, a data output and a byte clock input for receiving a byte clock signal causing loading of data at said data input into said memory cells; a calculation means having a data outputs coupled to said data inputs of said CRC checksum register and having data inputs coupled to said data outputs of said CRC checksum register and having a raw data input, said calculation means for accepting input data from said CRC checksum register and raw input data bytes at said raw data input and for dividing said raw input data by a predetermined bit pattern and for storing the remainder of said division in said CRC checksum register as said CRC check bits; and ignoring means coupled to said calculation means for causing said calculation means to ignore designated bits in said raw input data while performing said CRC calculation.
Claim 3
Dependent Claim
165 words
An apparatus as defined in claim 1 wherein said calculation means includes a plurality of rows of shifting links, each shifting link having an input and an output, with one said row for each input data bit, and wherein each shifting link row has its inputs coupled to the outputs of the next least significant shifting links in the previous row except for the least significant shifting link in each row which has its input coupled to the output of the most significant shifting link in the preceding row and except for the first row which has its inputs coupled to said data outputs of said CRC checksum register as if said CRC checksum register were a preceding row of shifting links, and wherein the last row of shifting links has its data outputs coupled to said data inputs of said CRC checksum register and wherein predetermined shifting links are gates which perform an exclusive-OR logical operation between their input bits and a predetermined signal.
Claim 4
Dependent Claim
61 words
An apparatus as defined in claim 2 wherein there is a predetermined signal for each said row of said shifting links and each said predetermined signal is generated by an input gate corresponding to that particular row which performs a predetermined logical operation between a predetermined one of said CRC bits and a data bit from said raw input data byte.
Claim 5
Dependent Claim
117 words
An apparatus as defined in claim 3 wherein the input gate corresponding to the first row is a gate which performs an exclusive-OR logical operation between the most significant CRC bit stored in said CRC checksum register and the first raw input data bit which would arrive if the data were input in serial fashion, and wherein the input gate corresponding to the second row is a gate which performs an exclusive-OR operation between the next most significant CRC bit stored in said CRC checksum register and the second raw input data bit which would arrive if said raw input data were input in a serial fashion and so on for each row of said shifting links.
Claim 6
Dependent Claim
249 words
The apparatus of claim 4 wherein said ignoring means comprises; preset means having inputs and having outputs, each said input coupled to a data output of said CRC checksum register, each said output coupled to a data input of said calculation means and, upon receipt of a NEW PRESET signal, for forcing a logic 1 to be received by each said data input of said calculation means; a first plurality of OR gates, one said OR gate designated for each row in said array of shifting links. and each said OR gate having its output coupled to an input of said input gate designated for the same row, and each OR gate having a first input for receiving the designated raw input data bit for that row, and having a second input for receiving an IGNORE X signal indicating when the raw input data bit for the designated row is to be ignored in the CRC calculation; and a second plurality of OR gates, one said OR gate designated for each row in said array of shifting links, and each said OR gate having a first input coupled to the output of said input gate for the designated row and having a second input for receiving an IGNORE X signal indicating when the raw input data bit for the designated row is to be ignored in the CRC calculation, and having an output coupled to the input for the least significant bit position shifting link in the designated row.
Claim 7
Independent Claim
205 words
An apparatus for calculating CRC bits on a data packet comprised of a plurality of bytes of data where one or more bits in the first byte may be excluded from the CRC calculation comprising: first means for storing the calculated CRC bits; second means coupled to said first means and having a raw data input for receiving bytes of raw input data, for receiving data stored in said first means and logically operating on it with said raw input data in an array of rows of shifting links, one said row being designated for each bit of a byte of said raw input data, so that the raw input data is divided by a predetermined binary number and the remainder is stored in said first means as said CRC bits; third means for forcing the data received by said second means from said first means to be all logic 1's at the beginning of the CRC calculation: and fourth means coupled between each bit of the raw input data byte and the row designated for that bit for forcing the row for each bit to be ignored in the CRC calculation to be logically transparent and pass all logic 1's to the next row.
Claim 8
Independent Claim
205 words
An apparatus for calculating CRC bits on a data packet comprised of a plurality of bytes of data where one or more bits in the first byte may be excluded from the CRC calculation comprising: first means for storing the calculated CRC bits; second means coupled to said first means and having a raw data input for receiving bytes of raw input data, for receiving data stored in said first means and logically operating on it with said raw input data in an array of rows of shifting links, one said row being designated for each bit of a byte of said raw input data, so that the raw input data is divided by a predetermined binary number and the remainder is stored in said first means as said CRC bits; third means for forcing the data received by said second means from said first means to be all logic 1's at the beginning of the CRC calculation: and fourth means coupled between each bit of the raw input data byte and the row designated for that bit for forcing the row for each bit to be ignored in the CRC calculation to be logically transparent and pass all logic 1's to the next row.
Claim 9
Dependent Claim
142 words
For a data packet comprised of a plurality of data bytes with the first data byte having one or more initial, consecutive bits which are to be ignored in making the CRC calculation, a method of calculating said CRC bits and ignoring said initial bits comprising the steps of: forcing all logic 1's as initial input data for the CRC calculation array comprised of a plurality of rows of shifting links, one row being designated for each bit in a byte of input data; forcing each row of shifting links, said row corresponding to one of said initial, consecutive bits to be ignored, to be logically transparent and pass said logic 1's generated in the first step to the next row; and calculating said CRC bits starting at the first row in said array which has not been forced to be transparent.
Claim 10
Dependent Claim
142 words
For a data packet comprised of a plurality of data bytes with the first data byte having one or more initial, consecutive bits which are to be ignored in making the CRC calculation, a method of calculating said CRC bits and ignoring said initial bits comprising the steps of: forcing all logic 1's as initial input data for the CRC calculation array comprised of a plurality of rows of shifting links, one row being designated for each bit in a byte of input data; forcing each row of shifting links, said row corresponding to one of said initial, consecutive bits to be ignored, to be logically transparent and pass said logic 1's generated in the first step to the next row; and calculating said CRC bits starting at the first row in said array which has not been forced to be transparent.
Claim 11
Dependent Claim
167 words
The method of claim 7 wherein a CRC checksum register is used to store the CRC bits and an array of rows of shifting links is used to calculate the CRC bits some of said shifting links being conductors and others being exclusive-OR gates having one input coupled to said CRC checksum register and another input coupled to an input gate which performs an exclusive-OR function between one of the bits in the most significant CRC byte stored in the CRC checksum register and one of the bits in the byte of raw input data, and wherein the step of forcing specified rows to be transparent includes the step of forcing the input of said input gate coupled to said bit of raw input data to be a logic 1 such that the result of the exclusive-OR operation in the input gate is a logic 0 which forces all the exclusive-OR gates in the rows for which this forcing step is carried out to become logically transparent.
Claim 12
Dependent Claim
101 words
The method of claim 8 wherein the output of said input gates are coupled to the input of the least significant shifting link in the next row through an OR gate having its output coupled to the input of the least significant shifting link in the next row, and further comprising the step of forcing the output of said OR gate to be a logic 1 for every row corresponding to one of said initial, consecutive raw input data bits to be ignored so that a logic 1 is passed on to the least significant shifting link in the next row.
References Cited (Backward Citations)
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