Patent US5305272A successfully refreshed from Google Patents.
US5305272A
Expired / Lapsed
US
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Sense amplifier circuit
Assignee: Toshiba Corp
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Filing: 1993-08-25
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Granted: 1994-04-19
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Expires: 2013-08-25
Abstract
Abstract In a sense amplifier circuit, an output potential is set in a data output state when an operation of the sense amplifier is a worst pass before the start of read access. In a memory read mode, when data corresponding to the worst-pass operation of the sense amplifier circuit is read out, the circuit is previously set in a corresponding data output state. A time delay (gate delay) by a gate does not occur. In contrast, when data corresponding to the best-pass operation of the sense amplifier circuit is read out, the gate delay occurs by this operation. The gate delay, however, is shorter than that of the worst pass. As a result, only the best pass is present as the operation mode of the sense amplifier circuit. Therefore, a high operation speed is achieved, so that a high read speed of the entire memory is achieved.
Inventors
- 👤 Kenji Matsuo
- 👤 Yasukazu Noine
- 👤 Kazuhiko Kasai
- 👤 Yoshihiro Kato
- 👤 Kazuaki Umetsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C7/00; G11C7/10; G11C7/1048; G11C11/417; G11C11/419; G11C7/06; G11C7/062
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
367 words
A sense amplifier circuit comprising: a first bit line supplied with a signal; a second bit line supplied with a signal complementary to said signal supplied to said first bit line; a circuit output terminal; a first transistor of a first conductivity type, having a gate and a current path, the gate being connected to said first bit line, and one terminal of the current path being connected to a first power source; a second transistor of said first conductivity type, having a gate and a current path, the gate being connected to said second bit line, and one terminal of the current path being connected to said first power source; a third transistor of a second conductivity type, having a gate and a current path, the gate and one terminal of the current path being connected to another terminal of said current path of said first transistor of the first conductivity type, and the other terminal of the current path being connected to a second power source; a fourth transistor of said second conductivity type, having a gate and a current path, one terminal of the current path being connected to another terminal of said current path of said second transistor of the first conductivity type and said circuit output terminal, the other terminal of the current path being connected to said second power source, and the gate being connected to the gate of said third transistor of the second conductivity type; and an output potential setting circuit for setting a potential on said circuit output terminal before data read access so that an output logic level of the circuit output terminal becomes a logic level appearing on the circuit output terminal when the sense amplifier circuit presents a worst-pass operation, the output potential setting circuit comprising a fifth transistor of said first conductivity type, having a gate and a current path, the current path being connected between said circuit output terminal and said first power source, and the gate being supplied with a precharge signal of said bit lines to render the fifth transistor conductive so that said circuit output terminal is set to a potential of said first power source before data read access.
Claim 2
Dependent Claim
367 words
A sense amplifier circuit comprising: a first bit line supplied with a signal; a second bit line supplied with a signal complementary to said signal supplied to said first bit line; a circuit output terminal; a first transistor of a first conductivity type, having a gate and a current path, the gate being connected to said first bit line, and one terminal of the current path being connected to a first power source; a second transistor of said first conductivity type, having a gate and a current path, the gate being connected to said second bit line, and one terminal of the current path being connected to said first power source; a third transistor of a second conductivity type, having a gate and a current path, the gate and one terminal of the current path being connected to another terminal of said current path of said first transistor of the first conductivity type, and the other terminal of the current path being connected to a second power source; a fourth transistor of said second conductivity type, having a gate and a current path, one terminal of the current path being connected to another terminal of said current path of said second transistor of the first conductivity type and said circuit output terminal, the other terminal of the current path being connected to said second power source, and the gate being connected to the gate of said third transistor of the second conductivity type; and an output potential setting circuit for setting a potential on said circuit output terminal before data read access so that an output logic level of the circuit output terminal becomes a logic level appearing on the circuit output terminal when the sense amplifier circuit presents a worst-pass operation, the output potential setting circuit comprising a fifth transistor of said first conductivity type, having a gate and a current path, the current path being connected between said circuit output terminal and said first power source, and the gate being supplied with a precharge signal of said bit lines to render the fifth transistor conductive so that said circuit output terminal is set to a potential of said first power source before data read access.
Claim 3
Dependent Claim
370 words
A sense amplifier circuit comprising: first and second bit lines; first and second sense amplifiers for amplifying a voltage between said first and second bit lines; a circuit output terminal; a first transistor of a first conductivity type, having a gate and a current path, the gate being connected to an output terminal of said first sense amplifier, and one terminal of the current path being connected to a first power source; a second transistor of said first conductivity type, having a gate and a current path, the gate being connected to an output terminal of said second sense amplifier and one terminal of the current path being connected to said first power source; a third transistor of a second conductivity type, having a gate and a current path, the gate and one terminal of the current path being connected to another terminal of said current path of said first transistor of the first conductivity type, and the other terminal of the current path being connected to a second power source; a fourth transistor of said second conductivity type, having a gate and a current path, one terminal of the current path being connected to another terminal of said current path of said second transistor of the first conductivity type and said circuit output terminal, the other terminal of the current path being connected to said second power source, and the gate being connected to the gate of said third transistor of the second conductivity type; and an output potential setting circuit for setting a potential on said circuit output terminal before data read access so that an output logical level of the circuit output terminal becomes a logic level appearing on the circuit output terminal when the sense amplifier circuit presents a worst-pass operation, the output potential setting circuit comprising a fifth transistor of said first conductivity type, having a gate and a current path, the current path being connected between said circuit output terminal and said first power source, and the gate being supplied with a precharge signal of said bit lines to render the fifth transistor conductive so that said circuit output terminal is set to a potential of said first power source before data read access.
Claim 4
Dependent Claim
370 words
A sense amplifier circuit comprising: first and second bit lines; first and second sense amplifiers for amplifying a voltage between said first and second bit lines; a circuit output terminal; a first transistor of a first conductivity type, having a gate and a current path, the gate being connected to an output terminal of said first sense amplifier, and one terminal of the current path being connected to a first power source; a second transistor of said first conductivity type, having a gate and a current path, the gate being connected to an output terminal of said second sense amplifier and one terminal of the current path being connected to said first power source; a third transistor of a second conductivity type, having a gate and a current path, the gate and one terminal of the current path being connected to another terminal of said current path of said first transistor of the first conductivity type, and the other terminal of the current path being connected to a second power source; a fourth transistor of said second conductivity type, having a gate and a current path, one terminal of the current path being connected to another terminal of said current path of said second transistor of the first conductivity type and said circuit output terminal, the other terminal of the current path being connected to said second power source, and the gate being connected to the gate of said third transistor of the second conductivity type; and an output potential setting circuit for setting a potential on said circuit output terminal before data read access so that an output logical level of the circuit output terminal becomes a logic level appearing on the circuit output terminal when the sense amplifier circuit presents a worst-pass operation, the output potential setting circuit comprising a fifth transistor of said first conductivity type, having a gate and a current path, the current path being connected between said circuit output terminal and said first power source, and the gate being supplied with a precharge signal of said bit lines to render the fifth transistor conductive so that said circuit output terminal is set to a potential of said first power source before data read access.
Claim 5
Dependent Claim
43 words
A sense amplifier circuit according to claim 1 or 2, wherein said first, second and fifth transistors of the first conductivity type are N channel MOS transistors, and said output terminal is set to a low level after the bit lines are precharged.
Claim 6
Dependent Claim
43 words
A sense amplifier circuit according to claim 1 or 2, wherein said first, second and fifth transistors of the first conductivity type are P channel MOS transistors, and said output terminal is set to a high level after the bit lines are precharged.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-18 | 1997-10-18 | 1998-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-18 | 2001-10-18 | 2002-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-18 | 2005-10-18 | 2006-04-19 | $7700.00 | Window Closed / Lapsed |