Semiconductor memory device having stacked capacitor cell

Claim 1

A semiconductor memory device having a stacked capacitor cell, comprising: a semiconductor substrate; a field oxide film and a gate oxide film which are formed on said semiconductor substrate; a gate electrode which is formed on each of said field oxide and said gate oxide film; impurity diffusion layers which are formed in said semiconductor substrate and which, together with said gate electrode, for a MOS transistor; an insulation layer which partly covers said MOS transistor and has a window; a storage electrode with a storage electrode contact is in contact with window, said storage electrode having, as a part thereof, a first electroconductive film which surrounds said window circumferentially and, as another part thereof, a second electroconductive film which is in contact with said first electroconductive film at least on its inside portion and also with said window; and a side wall of an oxide film which Is in contact with said window receiving said storage electrode, with each of side portions of said gate electrode and with an inner periphery of said first electroconductive film surrounding said window circumferentially and forming the part of said storage electrode, wherein said storage electrode contact is self-aligned with respect to said gate electrode.