US5304833A
Expired / Lapsed
US
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Complementary MOS semiconductor device
Assignee: Mitsubishi Electric Corp
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Filing: 1990-09-10
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Granted: 1994-04-19
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Expires: 2010-09-10
Abstract
Abstract To improve resistance to latch-up of complementary MOS semiconductor device, a high concentration buried layer (16) of same conduction type as a semiconductor substrate (1) and of concentration higher than the silicon semiconductor substrate is formed under a well region (5) of first conduction type in which MOS transistor of second conduction type is formed and a well region (3) of second conduction type in which MOS transistor of first conduction type is formed. The high concentration buried layer (16) reduces parasitic resistance of the semiconductor substrate (1), suppresses transfer of carrier due to surge or the like applied from outside and inside, and inhibits the parasitic transistors (12)(13) from turning on.
Inventors
- 👤 Komori Shigeki
- 👤 Mitsui Katsuyoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:39
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
135 words
A complementary MOS semiconductor device comprising: a semiconductor substrate of a first conduction type; a high concentration buried layer of the first conduction type having an impurity concentration higher than said semiconductor substrate; a well region of the first conduction type formed on one main surface of said semiconductor substrate located on upper side of said high concentration buried layer and in which an MOS transistor of a second conduction type is formed; and a well region of the second conduction type formed on said one main surface of the semiconductor substrate located on an upper side of said high concentration buried layer and in which an MOS transistor of the first conduction type is formed, at least one of said well regions being separated from said high concentration buried layer by said semiconductor substrate.
Claim 2
Dependent Claim
135 words
A complementary MOS semiconductor device comprising: a semiconductor substrate of a first conduction type; a high concentration buried layer of the first conduction type having an impurity concentration higher than said semiconductor substrate; a well region of the first conduction type formed on one main surface of said semiconductor substrate located on upper side of said high concentration buried layer and in which an MOS transistor of a second conduction type is formed; and a well region of the second conduction type formed on said one main surface of the semiconductor substrate located on an upper side of said high concentration buried layer and in which an MOS transistor of the first conduction type is formed, at least one of said well regions being separated from said high concentration buried layer by said semiconductor substrate.
Claim 3
Dependent Claim
42 words
A complementary MOS semiconductor device as set forth in claim 1, wherein said well region of the first conduction type is connected to a ground power source, while said well region of the second conduction type is connected to a voltage source.
Claim 4
Dependent Claim
35 words
A complementary MOS semiconductor device as set forth in claim 1, wherein said well region of the first conduction type and said well region of second conduction type are formed into a retrograde well structure.
Claim 5
Dependent Claim
24 words
A complementary MOS semiconductor device as set forth in claim 1, wherein said high concentration buried layer is a layer formed by ion implantation.
Claim 6
Dependent Claim
40 words
A complementary MOS semiconductor device as set forth in claim 1, wherein said well region of the first conduction type and said well region of the second conduction type are separated from the high concentration buried layer by the substrate.
References Cited (Backward Citations)
JPS5694670A
Cited
JPS5694672A
Cited
JPS5694671A
Cited
JPS6179250A
Cited
JPS6179247A
Cited
JPS6179249A
Cited
US5138420A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-18 | 1997-10-18 | 1998-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-18 | 2001-10-18 | 2002-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-18 | 2005-10-18 | 2006-04-19 | $7700.00 | Window Closed / Lapsed |