High performance array multiplier using four-to-two composite counters

Claim 1

A computing apparatus, comprising, input means for receiving a multiplier and a multiplicand and for supplying partial product terms of the multipler and multiplicand, a partial product reduction device for effecting partial product reduction of four partial products terms with a composite counter having a first pre-addition partial product addition counter stage and a second transmission partial product addition counter stage, the composite counter comprising two like four-to-two counter stages for pre-addition and for transmission addition, and wherein the like four-to-two counter stages each has five inputs, four of which are partial product terms and the other of which is a carry in, and wherein the first pre-addition partial product addition counter stage is a four-to-two counter having said five inputs, and having three outputs including a sum (S) at a weighted bit position (i), a second carry output (C) at a next adjacent weighted bit position for the more significant bit position (i-1) and a third carry output (C') provided to a next adjacent weighted more significant bit position (i-1); said first pre-addition partial product addition four-to-two counter stage receiving the partial product terms and reducing the partial product terms to two which are coupled to an arithmetic logic unit; said arithmetic logic unit coupled to said partial product reduction device, whereby the reduction of partial products to two is added by said arithmetic logic unit for producing results from a multiplication that can be used for subsequent processing in the apparatus.