Patent US5302908A successfully refreshed from Google Patents.
US5302908A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High precision phase comparator and phase locked loop
Assignee: NTT Docomo Inc
•
Filing: 1992-12-22
•
Granted: 1994-04-12
•
Expires: 2012-12-22
Abstract
Abstract A modulus counter counts first clock pulses to modulus M and outputs the count value as an m-bit reference signal, M being an integer. A latch circuit samples and holds the reference signal in response to a trigger signal generated by a trigger signal generator in synchronism with an input signal. A high-speed counter is supplied with second clock pulses of a frequency higher than that of the first clock pulses and starts counting the second clock pulses in response to the trigger signal and stops the counting in response to a first one of the first clock pulses immediately thereafter. A data processor converts the n-bit count value of the high-speed counter to n-bit data corresponding to a phase fraction of a phase quantization step in the latch, combines the n-bit data as low-order bits with m-bit data from the latch and outputs the combined data as phase difference data.
Inventors
- 👤 Yoshiaki Tarusawa
- 👤 Toshio Nojima
- 👤 Kazuaki Murota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 02:01
CPC Classifications
G; G01; G01R; G01R25/00; G01R25/08; H; H03; H03D; H03D13/00; H03D13/001; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/091; H03L7/16; H03L7/18; H03L7/183
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
183 words
A phase comparator comprising: first pulse generator means which generates first clock pulses of a first frequency; modulus counter means which counts said first clock pulses to modulus M and outputs the count value as a reference signal, said M being a positive integer; trigger signal generator means which generates a trigger signal synchronized with an input signal; latch means which responds to said trigger signal to sample and hold said count value of said modulus counter means; second pulse generator means which generates second clock pulses of a second frequency higher than said first frequency; high-speed counter means which counts said second clock pulses, said high-speed counter means starts counting of said second clock pulses in response to said trigger signal synchronized with said input signal and stops said counting in response to a first shot of said first clock pulses thereafter; and data processor means which generates phase difference data corresponding to a phase difference between said reference signal and said input signal, on the basis of data held in said latch means and counted data of said high-speed counter means.
Claim 2
Dependent Claim
183 words
A phase comparator comprising: first pulse generator means which generates first clock pulses of a first frequency; modulus counter means which counts said first clock pulses to modulus M and outputs the count value as a reference signal, said M being a positive integer; trigger signal generator means which generates a trigger signal synchronized with an input signal; latch means which responds to said trigger signal to sample and hold said count value of said modulus counter means; second pulse generator means which generates second clock pulses of a second frequency higher than said first frequency; high-speed counter means which counts said second clock pulses, said high-speed counter means starts counting of said second clock pulses in response to said trigger signal synchronized with said input signal and stops said counting in response to a first shot of said first clock pulses thereafter; and data processor means which generates phase difference data corresponding to a phase difference between said reference signal and said input signal, on the basis of data held in said latch means and counted data of said high-speed counter means.
Claim 3
Dependent Claim
46 words
The phase comparator of claim 1 which further includes power supply control means which responds to said trigger signal and the immediately following one of said first clock pulses to control the power supply to at least said high-speed counter means during its counting period alone.
Claim 4
Dependent Claim
33 words
The phase comparator of claim 2 wherein said power supply control means is adapted to supply power to said second pulse generator means during only said counting period of said high-speed counter means.
Claim 5
Dependent Claim
41 words
The phase comparator of claim 1 wherein said data processor means includes data transform means which transforms said counted data of said high-speed counter means into low-order bits corresponding to a fraction of said phase difference detected by said latch means.
Claim 6
Dependent Claim
115 words
The phase comparator of claim 1, 2, 3 or 4 which further includes digital-to-analog converter means for converting said phase difference data to an analog phase difference voltage corresponding to said phase difference, voltage controlled oscillator means whose oscillation frequency is controlled in accordance with said phase difference voltage, and programmable divider means which divides the oscillation output frequency of said voltage controlled oscillator means by an arbitrary integer and provides the frequency-divided output as said input signal to said trigger signal generator means, said digital-to-analog converter means, said voltage controlled oscillator means and said programmable divider means constituting a negative feedback loop whereby said input signal is synchronized in phase with said reference signal.
Claim 7
Dependent Claim
43 words
The phase comparator of claim 5 wherein said second pulse generator means is frequency multiplier means which frequency multiplies said first clock pulses from said first clock pulses from said first clock pulse generator means and outputs them as said second clock pulses.
Claim 8
Dependent Claim
36 words
The phase comparator of claim 5 wherein said second clock pulse generator means is signal converter means which outputs, as said second clock pulses, pulses synchronized with the oscillation output of said voltage controlled oscillator means.
Claim 9
Dependent Claim
27 words
The phase comparator of claim 5 wherein said negative feedback loop includes a loop filter connected in series to the output side of said data processor means.
References Cited (Backward Citations)
US4178631A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-11 | 1997-10-11 | 1998-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-11 | 2001-10-11 | 2002-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-11 | 2005-10-11 | 2006-04-12 | $7700.00 | Window Closed / Lapsed |