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US5302241A Expired / Lapsed US ⏱️ 0.0 years remaining

Post etching treatment of semiconductor devices

Assignee: Micron Technology Inc
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Filing: 1992-12-23
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Granted: 1994-04-12
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Expires: 2012-12-23
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Abstract

Abstract According to the process of this invention, after the etching of a semiconductor device in an etching area is completed a reactive chemical composition is typically formed on the semiconductor device. Prior to removing the etched semiconductor from the etching area, a passivating agent comprising silicon tetrafluoride is introduced into the etching area. The passivating agent reacts with any reactive chemical compound associated with the semiconductor to inhibit corrosion of the semiconductor device. The inhibited reactive chemical composition, which is typically in the gas phase, is then pumpable out of the etch area. The inhibited reactive chemical composition is substantially unreactive with and does not post-etch the semiconductor device as is the case with the reactive chemical composition per se. Furthermore, the parametric properties and the threshold voltage which were altered by the prior art dry etch process are not changed by the use of the subject post etching process.

Inventors

  • 👤 David A. Cathey, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 22:37
CPC Classifications
H; H10; H10P; H10P70/00; H10P70/20; H10P70/27; H10P70/273; Y; Y10; Y10S; Y10S438/00; Y10S438/976

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 130 words
An IC process of making, comprising: a) providing a semiconductor wafer, having an etching area comprising an exposed silicon dioxide surface, at least one expose metal line on the silicon dioxide surface, and an exposed photoresist surface that covers at least part of the top surface of the metal line; b) etching the wafer, in the etching area, using a compound containing bromine, the bromine reacting with the exposed surfaces of the photoresist layer, metal line, and silicon dioxide; c) completing the etching process, whereby the bromine superadjacent to exposed surfaces in the etching area; and d) exposing the bromine on the etching area surfaces to silicon tetrafluoride (SiF4), in an amount that replaces bromine, whereby the fluorine will not corrode the exposed etching area surfaces when exposed to moisture.
Claim 2
Dependent Claim 130 words
An IC process of making, comprising: a) providing a semiconductor wafer, having an etching area comprising an exposed silicon dioxide surface, at least one expose metal line on the silicon dioxide surface, and an exposed photoresist surface that covers at least part of the top surface of the metal line; b) etching the wafer, in the etching area, using a compound containing bromine, the bromine reacting with the exposed surfaces of the photoresist layer, metal line, and silicon dioxide; c) completing the etching process, whereby the bromine superadjacent to exposed surfaces in the etching area; and d) exposing the bromine on the etching area surfaces to silicon tetrafluoride (SiF4), in an amount that replaces bromine, whereby the fluorine will not corrode the exposed etching area surfaces when exposed to moisture.

References Cited (Backward Citations)

US4325984A Cited
US4325984B1 Cited
US4325984B2 Cited
US4505782A Cited
US4581101A Cited
US4592800A Cited
US4734157A Cited
US4985113A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-04-11 1997-10-11 1998-04-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-04-11 2001-10-11 2002-04-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-04-11 2005-10-11 2006-04-12 $7700.00 Window Closed / Lapsed

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