Microprocessor having waiting function

Claim 2

A microprocessor capable of executing a micro-instruction output from a micro-memory according to an address which corresponds to an instruction to be executed at a time when each time said microprocessor receives said address, said microprocessor comprising: control signal generating means for generating a control signal for a period of time corresponding to a period of time of a waiting signal at a time when said waiting signal is received from the outside; and address holding means connected to said control signal generating means for holding an address supplied to said micro-memory for a period of time corresponding to a period of time of said control signal, said control signal generating means including a plurality of signal generators, said plurality of signals generators including a T1 cycle signal generator capable of outputting a high-level T1 state signal indicating that a machine cycle is a T1 cycle during one period starting at a next leading edge of a system clock, said plurality of signal generators further including a T2 cycle signal generator capable of outputting a high-level T2 state signal indicating that said machine cycle stays at a T2 cycle during one period starting at a next leading edge of said system clock at a time when said high-level T1 state signal is output, said T2 cycle signal generator failing to output a T2 state signal in the case that a low-level waiting signal is given from an external source to said microprocessor, said T2 cycle signal generator being further capable of outputting said high-level T2 state signal during one period of said system clock after said waiting signal is returned to a high-level state.

Claim 3

A microprocessor capable of executing a micro-instruction output from a micro-memory according to an address which corresponds to an instruction to be executed at a time when each time said microprocessor receives said address, said microprocessor comprising: control signal generating means for generating a control signal for a period of time corresponding to a period of time of a waiting signal at a time when said waiting signal is received from the outside; and address holding means connected to said control signal generating means for holding an address supplied to said micro-memory for a period of time corresponding to a period of time of said control signal, said control signal generating means including a plurality of signal generators, said plurality of signal generators including a T1 cycle signal generator capable of outputting a high-level T1 state signal indicating that a machine cycle is a T1 cycle during one period starting at a next leading edge of a system clock, said plurality of signal generators further including a T2 cycle signal generator capable of outputting a high-level T2 state signal indicating that said machine cycle stays at a T2 cycle during one period starting at a next leading edge of said system clock at a time when said high-level T2 state signal is output, said plurality of signal generators further including a TW cycle signal generator capable of generating an internal waiting signal, said internal waiting signal being risen in synchronization to a tailing edge of a next T1 state signal at a time when said waiting signal drops, and said internal waiting signal being dropped in synchronization with a leading edge of a next system clock after said waiting signal returns to a high level.

Claim 4

A microprocessor capable of executing a micro-instruction output from a micro-memory according to an address which corresponds to an instruction to be executed at a time when each time said microprocessor receives said address, said microprocessor comprising: control signal generating means for generating a control signal for a period of time corresponding to a period of time of a waiting signal at a time when said waiting signal is received from the outside; and address holding means connected to said control signal generating means for holding an address supplied to said micro-memory for a period of time corresponding to a period of time of said control signal, said control signal generating means including a plurality of signal generators, said plurality of signal generators including a T1 cycle signal generator capable of outputting a high-level T1 state signal indicating that a machine cycle is a T1 cycle during one period starting at a next leading edge of a system clock, said plurality of signal generators further including a T2 cycle signal generator capable of outputting a high-level T2 state signal indicating that said machine cycle stays at a T2 cycle during one period starting at a next leading edge of said system clock at a time when said high-level T2 state signal is output, said plurality of signal generators further including a TW cycle signal generator capable of generating an internal waiting signal, said internal waiting signal being risen in synchronization to a tailing edge of a next T1 state signal at a time when said waiting signal drops, and said internal waiting signal being dropped in synchronization with a leading edge of a next system clock after said waiting signal returns to a high level.

Claim 5

A microprocessor according to claim 2, wherein said TW cycle signal generator is further capable of outputting a waiting state signal indicating that said machine cycle is a waiting cycle, said waiting state signal changing in the same manner as that of said internal waiting signal.