Picture editing apparatus in a digital still video camera system

Claim 2

A picture editing apparatus in a digital still video camera system, comprising: means for storing a plurality of digital signals in frames in a memory card; means for processing said digital video signals read-out from said memory card; image data address generator means for generating image data addresses of said memory card; one frame address generator means for generating a first picture assignment address of said memory card for one picture per each frame; multi-picture address generator means for generating second picture assignment addresses of a specified number of pictures recorded in said memory card; and picture mixing address generator means for generating third picture assignment addresses for selected pictures by mutually mixing a plurality of said selected pictures.

Claim 3

The picture editing apparatus as claimed in claim 1, further comprising synchronous signal generator means for controlling a time period of said image data addresses to be common to said storing and processing means.

Claim 4

The picture editing apparatus as claimed in claim 2, wherein said first picture assignment address, said second picture assignment addresses and said third picture assignment addresses become synchronized to a clock signal from said synchronous signal generator means.

Claim 5

The picture editing apparatus as claimed in claim 3, further comprising system control means for controlling said one frame address generator means, said multi-picture address generator means, said picture mixing address generator means and said synchronous signal generator means.

Claim 6

The picture editing apparatus as claimed in claim 4, further comprising selection means for alternately selecting said first, second and third picture assignment addresses in dependence upon a display mode of said picture editing apparatus.

Claim 7

The picture editing apparatus as claimed in claim 5, wherein said picture mixing address generator means comprises: latch means controlled by said system control means, for alternately selecting said third picture assignment addresses; control signal generator means for generating a control signal to synchronize said third picture assignment addresses to a clock signal of said synchronous signal generator means; and transfer means for transferring said third picture assignment addresses to said selection means.

Claim 8

The picture editing device as claimed in claim 6, wherein said picture mixing address generator further comprises: mixing picture number detection means for detecting a mixing picture number according to a counting of said clock signal, to generate a detected mixing number signal; and control means for selecting said detected mixing number signal in response to a picture mixing control signal from said system control means, and for controlling a counting period of said clock signal in accordance with said detected mixing number signal.

Claim 9

The picture editing apparatus as claimed in claim 5, wherein each of said image data addresses corresponds to pixel data of one of said digital video signals of a picture corresponding to said first, second and third picture assignment addresses.

Claim 10

The picture editing apparatus as claimed in claim 5, wherein said selection means comprises a multiplexer.

Claim 11

The picture editing apparatus as claimed in claim 6, wherein said image data address generator means comprises: reference signal counting means for generating an one frame reference signal by using a double counting stage when a vertical synchronous signal from said synchronous signal generator means is received; logic means for shaping a pulse in conjunction with said one frame reference signal to generate a shaped reference signal; and address counting means for generating a counting result of one of said image data addresses in conjunction with said clock signal received from said synchronous signal generator means and said shaped reference signal.

Claim 12

The picture editing apparatus as claimed in claim 8, wherein said selection means comprises a multiplexer.

Claim 13

A picture editing apparatus used in a still video camera for mixing a multiple of pictures during a reproduction mode, said picture editing apparatus comprising: memory means for storing a plurality of digital video signals by frames, each of said plurality of digital video signals representing a picture; reproduction buffer memory means for receiving said plurality of digital video signals from said memory means; one frame address generation means for generating a first picture assignment address signal when only one of said plurality of digital video signals is to be written from said memory means to said reproduction buffer memory means; multiple picture address generation means for generating a second picture assignment address signal when a multiple of digital video signals are to be written from said memory means to said reproduction buffer memory means; picture mixing address generation means for generating a third picture assignment address signal when a number of said plurality of digital video signals are to be mixed by superimposition; image data address generation means for generating an image data address signal representing addresses, in pixels, of picture data to be written to said reproduction buffer memory means synchronization generation means; for synchronizing the mixing of said number of said plurality of digital video signals by generating a clock signal; and first multiplexing means for enabling transmission of one of said first, second and third picture assignment address signals.

Claim 14

A picture editing apparatus used in a still video camera for mixing a multiple of pictures during a reproduction mode, said picture editing apparatus comprising: memory means for storing a plurality of digital video signals by frames, each of said plurality of digital video signals representing a picture; reproduction buffer memory means for receiving said plurality of digital video signals from said memory means; one frame address generation means for generating a first picture assignment address signal when only one of said plurality of digital video signals is to be written from said memory means to said reproduction buffer memory means; multiple picture address generation means for generating a second picture assignment address signal when a multiple of digital video signals are to be written from said memory means to said reproduction buffer memory means; picture mixing address generation means for generating a third picture assignment address signal when a number of said plurality of digital video signals are to be mixed by superimposition; image data address generation means for generating an image data address signal representing addresses, in pixels, of picture data to be written to said reproduction buffer memory means synchronization generation means; for synchronizing the mixing of said number of said plurality of digital video signals by generating a clock signal; and first multiplexing means for enabling transmission of one of said first, second and third picture assignment address signals.

Claim 15

The picture editing apparatus as claimed in claim 12, wherein said picture mixing address generation means comprises: first counting means for generating a counted synchronization signal by making counts of said clock signal from said synchronization generation means; latch means for alternately transmitting picture assignment addresses to generate said third picture assignment address signal; control signal generation means for synchronizing said third picture assignment address signal with said clock signal by generating a synchronizing signal in response to said counted synchronization signal; second multiplexing means for enabling transmission of said third picture address signal in response to said synchronizing signal; mixing picture number detection means for detecting numbers of pictures to be mixed based on said counted synchronization signal to generate a detected picture number signal; and third multiplexing means for selectively enabling transmission of said detected picture number signal, and for clearing said counts for said first counting means.

Claim 16

The picture editing apparatus as claimed in claim 13, wherein said latch means comprises a plurality of latches, each of said latches corresponding to one of said pictures stored in said memory means.

Claim 17

The picture editing apparatus as claimed in claim 13, wherein said mixing picture number detection means has a plurality of gates, a total number of gates being one less than a total number of pictures stored in said memory means, each of said gates corresponding to a picture mixing number.

Claim 18

The picture editing apparatus as claimed in claim 15, wherein said control signal generation means comprises a plurality of gates, a total number of gates of said control signal generation means equal to the total number of gates of said mixing picture number detection means.

Claim 19

The picture editing apparatus as claimed in claim 13, further comprising said third multiplexing means clearing said first counting means when said detected picture number signal is substantially the same as a selection control signal from a system controller.

Claim 20

The picture editing apparatus as claimed in claim 13 wherein said synchronization generation means comprises: reference clock generation means for generating said clock signal; and synchronization generator means for generating horizontal and vertical synchronous signals synchronized with said clock signal.

Claim 21

The picture editing apparatus as claimed in claim 16, wherein said synchronization generation means comprises: reference clock generation means for generating said clock signal; and synchronization generator means for generating horizontal and vertical synchronous signals synchronized with said clock signal.

Claim 22

The picture editing apparatus as claimed in claim 13, wherein said image data address generation means comprises: reference signal counting means for generating an one frame reference signal by double counting a vertical synchronous signal received from said synchronization generation means; logic means for shaping said one frame reference signal to generate a shaped one frame reference signal; second counting means for counting said clock signal in conjunction with said shaped one frame reference signal to generate said image data address signal.

Claim 23

The picture editing apparatus as claimed in claim 20, wherein said logic means comprises: delay means for delaying said one frame reference signal; and a logic gate for receiving said one frame reference signal and said delayed signal to generate said shaped one frame reference signal.

Claim 24

The picture editing apparatus as claimed in claim 19, wherein said image data address generation means comprises: reference signal counting means for generating an one frame reference signal by double counting said vertical synchronous signal; logic means for shaping said one frame reference signal to generate a shaped one frame reference signal; and second counting means for counting said clock signal in conjunction with said shaped one frame reference signal to generate said image data address signal.

Claim 25

The picture editing apparatus as claimed in claim 22, wherein said logic means comprises: delay means for delaying said one frame reference signal; and a logic gate for receiving said one frame reference signal and said delayed signal to generate said shaped one frame reference signal.

Claim 30

The method as claimed in claim 24, wherein said step of generating an image data address comprises: generating a clock signal; generating a synchronous signal in response to said clock signal and a read control signal from a system controller; counting a predetermined number of pulses of said synchronous signal to generate a counting signal; delaying said counting signal to generate a delayed signal; gating said delayed signal with said counting signal to generate a clearing signal; and counting said clock signal in dependence upon said clearing signal to generate said image data address.

Claim 31

The method as claimed in claim 25, wherein said step of generating an image data address comprises: generating a clock signal; generating a synchronous signal in response to said clock signal and a read control signal from a system controller; counting a predetermined number of pulses of said synchronous signal to generate a counting signal; delaying said counting signal to generate a delayed signal; gating said delayed signal with said counting signal to generate a clearing signal; and counting said clock signal in dependence upon said clearing signal to generate said image data address.

Claim 32

A picture editing apparatus used in a still video camera for mixing a multiple of pictures during a reproduction mode, said picture editing apparatus comprising: memory means for storing a plurality of digital video signals by frames, each of said plurality of digital video signals representing a picture; reproduction buffer memory means for receiving said plurality of digital video signals from said memory means; picture mixing address generation means for generating a picture assignment address signal indicating locations of said multiple of pictures stored in said memory means, when a number of said plurality of digital video signals are to be mixed by superimposition; image data address generation means for generating an image data address signal representing addresses, in pixels, of picture data to be written to said reproduction buffer memory means; and synchronization generation means for synchronizing the mixing of said number of said plurality of digital video signals by generating a clock signal.

Claim 33

A picture editing apparatus used in a still video camera for mixing a multiple of pictures during a reproduction mode, said picture editing apparatus comprising: memory means for storing a plurality of digital video signals by frames, each of said plurality of digital video signals representing a picture; reproduction buffer memory means for receiving said plurality of digital video signals from said memory means; picture mixing address generation means for generating a picture assignment address signal indicating locations of said multiple of pictures stored in said memory means, when a number of said plurality of digital video signals are to be mixed by superimposition; image data address generation means for generating an image data address signal representing addresses, in pixels, of picture data to be written to said reproduction buffer memory means; and synchronization generation means for synchronizing the mixing of said number of said plurality of digital video signals by generating a clock signal.

Claim 34

The picture editing apparatus as claimed in claim 28, wherein said picture mixing address generation means comprises: first counting means for generating a counted synchronization signal by making counts of said clock signal from said synchronization generation means; latch means for alternately transmitting picture assignment addresses to generate said picture assignment address signal; control signal generation means for synchronizing said picture assignment address signal with said clock signal by generating a synchronizing signal in response to said counted synchronization signal; first multiplexing means for enabling transmission of said picture assignment address signal in response to said synchronizing signal; mixing picture number detection means for detecting numbers of pictures to be mixed based on said counted synchronization signal to generate a detected picture number signal; and second multiplexing means for selectively enabling transmission of said detected picture number signal, and for clearing said counts for said first counting means.

Claim 35

The picture editing apparatus as claimed in claim 29 wherein said image data address generation means comprises: reference signal counting means for generating an one frame reference signal by double counting a vertical synchronous signal received from said synchronization generation means; logic means for shaping said one frame reference signal to generate a shaped one frame reference signal; and second counting means for counting said clock signal in conjunction with said shaped one frame reference signal to generate said image data address signal.

Claim 36

The picture editing apparatus as claimed in claim 29 wherein said synchronization generation means comprises: reference clock generation means for generating said clock signal; and synchronization generator means for generating horizontal and vertical synchronous signals synchronized with said clock signal.