US5300823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Internal voltage dropping circuit for semiconductor device
Assignee: Sharp Corp
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Filing: 1992-07-14
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Granted: 1994-04-05
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Expires: 2012-07-14
Abstract
Abstract A control circuit for an internal voltage dropping circuit for a semiconductor load circuit includes a first transistor which turns on or off so as to permit or inhibit current from flowing in the internal voltage dropping circuit in accordance with an active/standby switch signal. A pulsating control signal having a specified duty ratio is generated and coupled to the control circuit while a semiconductor device in the load circuit is in a standby mode. The control circuit is intermittently activated at the specified duty ratio when the semiconductor device is on standby so that a current consumption can be reduced in accordance with the duty ratio.
Inventors
- 👤 Makoto Ihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:36
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
232 words
A control circuit for an internal voltage dropping circuit for a load including a semiconductor device, comprising pulse signal generating means for generating a pulse signal having a specified duty ratio, and switch means including an internal voltage dropping circuit connected to said pulse signal generating means and receiving a pulse signal produced by said pulse signal generating means to periodically activate said internal voltage dropping circuit in response to said pulse signal when the semiconductor device included in the load is on standby; said internal voltage dropping circuit further comprising, a mirror type differential amplifier having a reference voltage input coupled to one side thereof and a supply voltage output, a first output transistor having a control electrode coupled to the other side of said differential amplifier and one current conduction electrode coupled between a supply voltage and said supply voltage output, first circuit means coupling to said pulse signal and including a relatively low controlled current path coupled between said differential amplifier and ground potential, second circuit means coupled to an activate/standby signal and including a relatively high controlled current path coupled between said differential amplifier and ground potential, and a second output transistor having a control electrode coupled to both said pulse signal and to said activate/standby signal and a pair of current conduction electrodes coupled between a supply voltage and the control electrode of said first output transistor.
Claim 2
Dependent Claim
232 words
A control circuit for an internal voltage dropping circuit for a load including a semiconductor device, comprising pulse signal generating means for generating a pulse signal having a specified duty ratio, and switch means including an internal voltage dropping circuit connected to said pulse signal generating means and receiving a pulse signal produced by said pulse signal generating means to periodically activate said internal voltage dropping circuit in response to said pulse signal when the semiconductor device included in the load is on standby; said internal voltage dropping circuit further comprising, a mirror type differential amplifier having a reference voltage input coupled to one side thereof and a supply voltage output, a first output transistor having a control electrode coupled to the other side of said differential amplifier and one current conduction electrode coupled between a supply voltage and said supply voltage output, first circuit means coupling to said pulse signal and including a relatively low controlled current path coupled between said differential amplifier and ground potential, second circuit means coupled to an activate/standby signal and including a relatively high controlled current path coupled between said differential amplifier and ground potential, and a second output transistor having a control electrode coupled to both said pulse signal and to said activate/standby signal and a pair of current conduction electrodes coupled between a supply voltage and the control electrode of said first output transistor.
Claim 3
Dependent Claim
46 words
The control circuit according to claim 1, wherein said pulse signal generating means includes an oscillator coupled to a binary counter circuit comprised of a plurality of series connected flip-flops, and wherein a first state flip-flop has an input connected to an output of said oscillator.
Claim 4
Dependent Claim
14 words
The control circuit according to claim 2 wherein said oscillator comprises a ring oscillator.
Claim 5
Dependent Claim
47 words
The control circuit according to claim 2 wherein each of said flip-flops includes an output and additionally including a multiple input binary logic gate including an input coupled to each said output of said flip-flops and having an output coupled to said relatively low controlled current path.
Claim 6
Dependent Claim
18 words
The control circuit according to claim 4 wherein said mirror type differential amplifier comprises a transistor differential amplifier.
Claim 7
Dependent Claim
47 words
The control circuit according to claim 6 wherein said relatively low controlled current path includes a current control transistor having a pair of current carrying electrodes coupled between said differential amplifier and ground potential and a control electrode coupled to the output of said binary logic gate.
Claim 8
Dependent Claim
17 words
The control circuit according to claim 6 wherein said logic gate comprises a coincidence type gate circuit.
Claim 9
Dependent Claim
36 words
The control circuit according to claim 6 wherein said logic gate comprises a NAND gate and additionally including a logic inverter coupled between an output of said NAND gate and the control electrode of said transistor.
Claim 10
Dependent Claim
43 words
The control circuit according to claim 4 wherein said relatively high controlled current path includes a current control transistor having a pair of current carrying electrode coupled between said differential amplifier and ground potential and a control electrode coupled to said activate/standby signal.
Claim 11
Dependent Claim
41 words
The control circuit according to claim 9 and additionally including another binary logic gate having a pair of inputs respectively coupled to said pulse signal and said activate/standby and an output coupled to the control electrode of said second output transistor.
Claim 12
Dependent Claim
18 words
The control circuit according to claim 10 wherein said another logic gate comprises a coincidence type gate circuit.
Claim 13
Dependent Claim
39 words
The control circuit according to claim 10 wherein said another logic gate comprises a NOR gate and additionally including a logic inverter coupled between an output of said NOR gate and the control electrode of said second output transistor.
Claim 14
Dependent Claim
30 words
The control circuit according to claim 1 wherein said mirror type differential amplifier includes a MOSFET type transistor circuit and said first and second output transistors comprise MOSFET type transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |