Plasticized polyetherimide adhesive composition and usage

Claim 2

A plasticized polyetherimide adhesive composition having a melt viscosity capable of providing substantially void free adhesive bonding at temperatures in the range of about 200° to 260° C. between overlay dielectric layer and substrate having at least one IC chip attached thereon, which plasticized polyetherimide composition comprises by weight, (A) 100 parts of a polyetherimide, and (B) 5 to 25 parts of a plasticizer.

Claim 3

A plasticized polyetherimide adhesive in accordance with claim 1, where the plasticizer is a bisphenol A dianhydride bis(alkyl or aryl bismide).

Claim 4

A plasticized polyetherimide adhesive in accordance with claim 1, where the plasticizer is pentaerythritol tetrabenzoate.

Claim 5

A plasticized polyetherimide adhesive in accordance with claim 1, where the plasticizer is triphenylphosphate.

Claim 6

A plasticized polyetherimide adhesive in accordance with claim 2, where the plasticizer is bisphenol A dianhydride bis(N-phenylimide).

Claim 7

A plasticized polyetherimide adhesive in accordance with claim 2, where the plasticizer is bisphenol A dianhydride bis(N-methylimide)

Claim 8

A plasticized polyetherimide adhesive in accordance with claim 2, where the plasticizer is bisphenol A dianhydride bis(N-butylimide).

Claim 9

A plasticized polyetherimide adhesive in accordance with claim 2, where the plasticizer is bisphenol A dianhydride bis(N-pyridylimide).

Claim 10

A high density interconnect circuit array comprising, (a) a substrate, (b) at least one integrated circuit chip with at least one interconnection pad disposed on the substrate, and (c) a laminate layer overlying and bridging the integrated circuit chip, where the laminate layer of (c) has a plurality of via openings, where at least one of the via openings is aligned with at least one of the interconnection pads of (b) and a pattern of interconnection conductors disposed on top of the laminate layer so as to extend between some of the openings to provide electrical connections between at least one of the interconnection pads through the openings, which laminate layer of (c) comprises a dielectric overlay layer and an adhesive layer in direct contact with the integrated chip, which adhesive layer comprises a plasticized polyetherimide having a melt viscosity sufficiently low to provide void free adhesive bonding at temperatures in the range of between 200° C. to 260° C. between the dielectric overlay layer and substrate having at least integrated circuit chip disposed thereon.

Claim 11

A high density interconnect circuit array comprising, (a) a substrate, (b) at least one integrated circuit chip with at least one interconnection pad disposed on the substrate, and (c) a laminate layer overlying and bridging the integrated circuit chip, where the laminate layer of (c) has a plurality of via openings, where at least one of the via openings is aligned with at least one of the interconnection pads of (b) and a pattern of interconnection conductors disposed on top of the laminate layer so as to extend between some of the openings to provide electrical connections between at least one of the interconnection pads through the openings, which laminate layer of (c) comprises a dielectric overlay layer and an adhesive layer in direct contact with the integrated chip, which adhesive layer comprises a plasticized polyetherimide having a melt viscosity sufficiently low to provide void free adhesive bonding at temperatures in the range of between 200° C. to 260° C. between the dielectric overlay layer and substrate having at least integrated circuit chip disposed thereon.

Claim 12

A high density interconnect circuit array in accordance with claim 9, having at least one additional laminate layer above the laminate layer of (c) comprising a dielectric layer and an adhesive layer.

Claim 13

A high density interconnect circuit array in accordance with claim 10, where the dielectric layer is a polyimide and the adhesive layer is a siloxane polyimide.