Patent US5299139A successfully refreshed from Google Patents.
US5299139A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Short locator method
Assignee: Cadence Design Systems Inc
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Filing: 1991-06-21
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Granted: 1994-03-29
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Expires: 2011-06-21
Abstract
Abstract An improved circuit layout-verifying system and method operates on a plurality of polygons that are representative of an electrical node to test the proper or improper connection of each polygon to another contiguous polygon and designates for display those polygons that represent improper connections between known or identified reference points on the node. Traversals along a sequence of contiguous polygons between known reference points on the same electrical node are designated as proper connections or successes, and traversals along a sequence of contiguous polygon between reference points associated with different electrical nodes are designated as improper connections or failures at least along a portion of the sequence. Data from all traversals of all polygons from all known reference points is then analyzed to remove unambiguous sequences of polygons for the improperly connected electrical nodes. High resolution analysis is performed on large, single electrical nodes by selectively breaking down the node into subpolygons that can be analyzed in the previous manner.
Inventors
- 👤 Allen Baisuck
- 👤 William W. Hoover, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:49
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
158 words
A computer implemented method for analyzing an electrical node of a circuit layout to locate erroneous connections thereon, the method comprising the steps of: forming a representation of the area of an electrical node including the erroneous connections therein for analysis; segregating the area of the electrical node into a plurality of individual polygons oriented in contiguous array within said area wherein said step of segregating includes the substeps of: identifying all obtuse angles along the perimeter of the area of the electrical node including the erroneous connections therein; and forming alternate substantially horizontal and vertical divisions of the area of the electrical node at the locations of the obtuse angles in selected sequence along the perimeter of said area to form thereby a plurality of individual polygons in contiguous array; and analyzing each individual polygon for proper connection to a contiguous polygon commencing from an initial starting point on a polygon within the area of the node.
Claim 2
Dependent Claim
158 words
A computer implemented method for analyzing an electrical node of a circuit layout to locate erroneous connections thereon, the method comprising the steps of: forming a representation of the area of an electrical node including the erroneous connections therein for analysis; segregating the area of the electrical node into a plurality of individual polygons oriented in contiguous array within said area wherein said step of segregating includes the substeps of: identifying all obtuse angles along the perimeter of the area of the electrical node including the erroneous connections therein; and forming alternate substantially horizontal and vertical divisions of the area of the electrical node at the locations of the obtuse angles in selected sequence along the perimeter of said area to form thereby a plurality of individual polygons in contiguous array; and analyzing each individual polygon for proper connection to a contiguous polygon commencing from an initial starting point on a polygon within the area of the node.
Claim 3
Dependent Claim
64 words
The method according to claim 1, wherein for any individual polygon, obtuse angles are identified; and substantially horizontal and vertical divisions are formed in alternate array along the perimeter thereof at the locations of the identified obtuse angles to form thereby a plurality of individual subpolygons in contiguous array with each other and with other individual polygons within the area of the electrical node.
Claim 4
Dependent Claim
52 words
The method according to claim 1, wherein the step of forming a representation comprises the steps of: retrieving connectivity information for said circuit layer, including information pertaining to the number of layers in said circuit layout and interconnections between said layers; and generating an internal data structure for holding said connectivity information.
Claim 5
Dependent Claim
37 words
The method according to claim 1, wherein the step of analyzing each individual polygon includes the step of designating a plurality of said polygons as reference points which are associated with at least two different electrical nodes.
Claim 6
Dependent Claim
39 words
The method according to claim 4, further comprising the step of: removing from a set of polygons to be analyzed any polygon which is not a reference point and which initially is connected to two or fewer other polygons.
Claim 7
Dependent Claim
208 words
A computer implemented method for analyzing an electrical node of a circuit layout to locate erroneous connections therein, the method comprising the steps of: forming a representation of the area of an electrical node including the erroneous connections therein for analysis; identifying a plurality of reference points in the area of the electrical node which are associated with at least two different electrical nodes; forming a plurality of contiguous polygons along and within the area of the electrical node at least between said reference points; traversing a sequence of polygons from one reference point toward another reference point on the electrical node to determine electrical connection of each polygon to an adjacent polygon previously traversed in the sequence, and storing the results of the determination for each polygon along the course of another reference point; designating success of connections in the stored results under conditions of the sequence proceeding between two reference points associated with the same electrical node, and designating failure of connections in the stored results under conditions of the sequence proceeding between two reference points associated with different electrical nodes; and displaying a representation of at least a portion of the sequence of polygons for which the stored results designate failure between two reference points.
Claim 8
Dependent Claim
208 words
A computer implemented method for analyzing an electrical node of a circuit layout to locate erroneous connections therein, the method comprising the steps of: forming a representation of the area of an electrical node including the erroneous connections therein for analysis; identifying a plurality of reference points in the area of the electrical node which are associated with at least two different electrical nodes; forming a plurality of contiguous polygons along and within the area of the electrical node at least between said reference points; traversing a sequence of polygons from one reference point toward another reference point on the electrical node to determine electrical connection of each polygon to an adjacent polygon previously traversed in the sequence, and storing the results of the determination for each polygon along the course of another reference point; designating success of connections in the stored results under conditions of the sequence proceeding between two reference points associated with the same electrical node, and designating failure of connections in the stored results under conditions of the sequence proceeding between two reference points associated with different electrical nodes; and displaying a representation of at least a portion of the sequence of polygons for which the stored results designate failure between two reference points.
Claim 9
Dependent Claim
135 words
The method according to claim 6 wherein the step of traversing includes traversing forward in the sequence of polygons newly encountered and designating any polygon associated with a junction to another electrical node, and traversing backward in the sequence of polygons upon condition of encountering a reference point associated with another electrical node, the backward traverse continuing from such another reference point at least to a polygon associated with a junction to designate the polygons in the backward traverse as failures of connections; traversing forward from the junction polygon along another sequence of polygons toward another reference point with designations of success of connections in the stored results for each polygon between the junction polygon and a reference point associated with the same electrical node; and displaying at least a representation of the junction polygon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-28 | 1997-09-27 | 1998-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-28 | 2001-09-27 | 2002-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-28 | 2005-09-27 | 2006-03-29 | $7700.00 | Window Closed / Lapsed |