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Patent US5298447A successfully refreshed from Google Patents.
US5298447A
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Method of fabricating a flash memory cell
Assignee: United Microelectronics Corp
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Filing: 1993-07-22
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Granted: 1994-03-29
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Expires: 2013-07-22
Abstract
Abstract A flash memory cell includes the usual thermal oxide layer deposited above the substrate including the source and the drain. On the thermal oxide layer, a silicon rich oxide layer is formed. Above the silicon rich oxide layer a gate structure is formed of layer of polysilicon separated by an intermediate dielectric layer. The lower polysilicon layer commences as an initial portion of the layer of small grain size followed by either amorphous or large grain size material.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:16
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/682; H10B; H10B69/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
129 words
A method of forming a self-aligned flash MOS field effect transistor structure on a silicon semiconductor substrate having an upper surface, a) forming a source region and a drain region in said substrate on said upper surface, b) forming a tunnel oxide structure over the surface of said substrate including the surface of said source and said drain regions, c) said tunnel oxide structure including a thermal oxide layer formed on the surface said substrate and a film of silicon rich oxide deposited upon said thermal oxide layer, and e) depositing a gate structure composed of a stack upon said silicon rich oxide film, said stack comprising a first polysilicon layer, a dielectric layer deposited upon said polysilicon layer and a second polysilicon layer deposited upon said dielectric layer.
Claim 2
Independent Claim
129 words
A method of forming a self-aligned flash MOS field effect transistor structure on a silicon semiconductor substrate having an upper surface, a) forming a source region and a drain region in said substrate on said upper surface, b) forming a tunnel oxide structure over the surface of said substrate including the surface of said source and said drain regions, c) said tunnel oxide structure including a thermal oxide layer formed on the surface said substrate and a film of silicon rich oxide deposited upon said thermal oxide layer, and e) depositing a gate structure composed of a stack upon said silicon rich oxide film, said stack comprising a first polysilicon layer, a dielectric layer deposited upon said polysilicon layer and a second polysilicon layer deposited upon said dielectric layer.
Claim 3
Dependent Claim
18 words
A method in accordance with claim 1 wherein said silicon rich oxide is deposited by chemical vapor deposition.
Claim 4
Dependent Claim
31 words
A method in accordance with claim 1 wherein said first polysilicon layer includes a lower portion composed of relatively smaller grain size crystals, and an upper portion composed of amorphous polysilicon.
Claim 5
Dependent Claim
18 words
A method in accordance with claim 3 wherein said silicon rich oxide is deposited by chemical vapor deposition.
Claim 6
Dependent Claim
37 words
A method in accordance with claim 1 wherein said first polysilicon layer includes a lower portion composed of relatively smaller grain size crystals, and an upper portion composed of a structure composed of larger grain size crystals.
Claim 7
Dependent Claim
18 words
A method in accordance with claim 5 wherein said silicon rich oxide is deposited by chemical vapor deposition.
Claim 8
Dependent Claim
48 words
A method in accordance with claim 5 wherein the thickness of said silicon rich oxide layer is within the range between about 50 Å and about 200 Å and the thickness of said thermal oxide layer is within the range between about 50 Å and about 100 Å.
Claim 9
Dependent Claim
18 words
A method in accordance with claim 7 wherein said silicon rich oxide is deposited by chemical vapor deposition.
Claim 10
Dependent Claim
52 words
A method in accordance with claim 5 wherein said lower portion of said first polysilicon layer is deposited by LPCVD at a temperature of about 630° C. and said upper portion of said first layer of polysilicon is deposited as amorphous phase silicon by LPCVD at a temperature of about 560° C.
Claim 11
Dependent Claim
48 words
A method in accordance with claim 9 wherein the thickness of said silicon rich oxide layer is within the range between about 50 Å and about 200 Å and the thickness of said thermal oxide layer is within the range between about 50 Å and about 100 Å.
Claim 12
Dependent Claim
18 words
A method in accordance with claim 9 wherein said silicon rich oxide is deposited by chemical vapor deposition.
Claim 13
Dependent Claim
29 words
A method in accordance with claim 9 wherein a native polyoxide is provided as a boundary between said lower portion and said upper portion of said first polysilicon layer.
Claim 14
Dependent Claim
48 words
A method in accordance with claim 12 wherein the thickness of said silicon rich oxide layer is within the range between about 50 Å and about 200 Å and the thickness of said thermal oxide layer is within the range between about 50 Å and about 100 Å.
Claim 15
Dependent Claim
18 words
A method in accordance with claim 12 wherein said silicon rich oxide is deposited by chemical vapor deposition.
Claim 16
Independent Claim
74 words
A method of forming a self-aligned flash MOS field effect transistor structure on a silicon semiconductor substrate with a source junction and a drain junction therein and said substrate having a surface a tunnel oxide structure deposited thereon, the improvement comprising, said tunnel oxide comprising a thermal oxide layer deposited upon said substrate and a silicon-rich-oxide layer deposited upon said thermal oxide layer, and a flash memory gate structure deposited upon said silicon-rich-oxide layer.
Claim 17
Independent Claim
74 words
A method of forming a self-aligned flash MOS field effect transistor structure on a silicon semiconductor substrate with a source junction and a drain junction therein and said substrate having a surface a tunnel oxide structure deposited thereon, the improvement comprising, said tunnel oxide comprising a thermal oxide layer deposited upon said substrate and a silicon-rich-oxide layer deposited upon said thermal oxide layer, and a flash memory gate structure deposited upon said silicon-rich-oxide layer.
Claim 18
Dependent Claim
48 words
A method in accordance with claim 1 wherein the thickness of said silicon rich oxide layer is within the range between about 50 Å and about 200 Å and the thickness of said thermal oxide layer is within the range between about 50 Å and about 100 Å.
Claim 19
Dependent Claim
18 words
A method in accordance with claim 16 wherein said silicon rich oxide is deposited by chemical vapor deposition.
Claim 20
Dependent Claim
18 words
A method in accordance with claim 15 wherein said silicon rich oxide is deposited by chemical vapor deposition.
References Cited (Backward Citations)
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