US5297271A
Expired / Lapsed
US
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Method and apparatus for performing a read-write-modify operation in a VGA compatible controller
Assignee: Valeo Thermique Moteur SA
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Filing: 1993-04-21
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Granted: 1994-03-22
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Expires: 2013-04-21
Abstract
Abstract A VGA controller with a read-modify-write cycle implemented therein is provided. By implementing the read-modify-write cycle in hardware, and by reducing the data for such operations to a single address source, read-modify-write operations can be performed in a single cycle, as opposed to separate read and write cycles, with a consequent improvement in overall operating speed.
Inventors
- 👤 Dhimant Bhayani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:41
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
166 words
In the operation of a video graphics array controller having a memory and a timing sequencer, said video graphics array controller being coupled to a CPU, a method for implementing a read-modify-write cycle comprising the steps of: enabling the read-modify-write cycle by setting a read-modify-write control bit for said sequencer; specifying a particular logical operation; said CPU generating a hardware request for a write operation to the video graphics array memory, said hardware request specifying a first operand value, and a video graphics array memory write address; said sequencer generating timing signals for a read-modify-write cycle when said control bit is set; reading a second operand value from the video graphics array memory write address; performing the particular logic operation on the first operand value and the second operand value to produce a result; and writing the result of performing the particular logic operation to the video graphics array memory write address, wherein said reading, performing, and writing steps all take place during said read-modify-write cycle.
Claim 2
Dependent Claim
166 words
In the operation of a video graphics array controller having a memory and a timing sequencer, said video graphics array controller being coupled to a CPU, a method for implementing a read-modify-write cycle comprising the steps of: enabling the read-modify-write cycle by setting a read-modify-write control bit for said sequencer; specifying a particular logical operation; said CPU generating a hardware request for a write operation to the video graphics array memory, said hardware request specifying a first operand value, and a video graphics array memory write address; said sequencer generating timing signals for a read-modify-write cycle when said control bit is set; reading a second operand value from the video graphics array memory write address; performing the particular logic operation on the first operand value and the second operand value to produce a result; and writing the result of performing the particular logic operation to the video graphics array memory write address, wherein said reading, performing, and writing steps all take place during said read-modify-write cycle.
Claim 3
Dependent Claim
67 words
The method of claim 1, wherein said method of implementing a read-modify-write cycle is performed during a graphics mode of said video graphics array controller, wherein said video graphics array memory comprises a plurality of memory planes accessible during said graphics mode, and wherein said steps of reading and writing apply a single address to all of said plurality of memory planes during said single read-modify-write cycle.
Claim 4
Independent Claim
192 words
An apparatus for performing a read-modify-write cycle in a video graphics array controller having a memory, said video graphics array controller being coupled to a CPU, the apparatus comprising: a timing sequencer coupled to said CPU; means for specifying a particular logical operation means for enabling the read-modify-write cycle by setting a read-modify-write control bit for said sequencer; means, coupled to said CPU, for receiving from said CPU a hardware request for a write operation to the video graphics array memory, said hardware request specifying a first operand value, and a video graphics array memory write address, said sequencer generating read-modify-write timing signals for a read-modify-write cycle when said control bit is set; means responsive to the read-modify-write timing signals and to said hardware request for reading a second operand value from the video graphics array memory write address during the read-modify-write cycle; means for performing the particular logic operation on the first operand value and the second operand value to produce a result during said read-modify-write cycle; and means for writing the result of performing the particular logic operation to the video graphics array memory write address during said read-modify-write cycle.
Claim 5
Independent Claim
192 words
An apparatus for performing a read-modify-write cycle in a video graphics array controller having a memory, said video graphics array controller being coupled to a CPU, the apparatus comprising: a timing sequencer coupled to said CPU; means for specifying a particular logical operation means for enabling the read-modify-write cycle by setting a read-modify-write control bit for said sequencer; means, coupled to said CPU, for receiving from said CPU a hardware request for a write operation to the video graphics array memory, said hardware request specifying a first operand value, and a video graphics array memory write address, said sequencer generating read-modify-write timing signals for a read-modify-write cycle when said control bit is set; means responsive to the read-modify-write timing signals and to said hardware request for reading a second operand value from the video graphics array memory write address during the read-modify-write cycle; means for performing the particular logic operation on the first operand value and the second operand value to produce a result during said read-modify-write cycle; and means for writing the result of performing the particular logic operation to the video graphics array memory write address during said read-modify-write cycle.
Claim 6
Dependent Claim
35 words
The apparatus of claim 3, wherein said apparatus for performing a read-modify-write cycle is configured to provide only a single address to said memory during said read-modify-write cycle, said single address being said write address.
Claim 7
Dependent Claim
53 words
The apparatus of claim 4, wherein said read-modify-write cycle is employed during a graphics mode of said video graphics array controller, wherein said video graphics array memory comprises a plurality of memory planes accessible during said graphics mode, and wherein said single address is applied to all of said plurality of memory planes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-21 | 1997-09-20 | 1998-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-21 | 2001-09-20 | 2002-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-21 | 2005-09-20 | 2006-03-22 | $7700.00 | Window Closed / Lapsed |