Image data processing apparatus

Claim 2

An image data processing apparatus for processing image data in a pipe line fashion, comprising: first and second address buses; a control bus; a first data bus; means for providing an input processing command; main control means for generating an access control instruction and a memory plane control instruction in response to said input processing command; access control means connected to said first and second address buses, said control bus, and said first data bus and operating in synchronism with machine cycles and in response to said access control instruction from said main control means, for selectively generating and respectively outputting onto said first and second address buses first and second addresses, and for generating and outputting onto said control bus read-modified-write control data; a first memory plane connected to said first address bus, said control bus, and said first data bus, and operating in synchronism with said machine cycles and in response to said memory plane control instruction from said main control means and said read-modified-write control data from said access control means, comprising: first memory plane memory means for outputting first image data stored at said first address over said first address bus at a first half of each machine cycle, and first memory plane data output means for outputting said first image data as first transfer data onto said first data bus at said first half of cycle, and a second memory plane connected to said second address bus, said control bus, and said first data bus, and operating in synchronism with said machine cycles and in response to said memory plane control instruction from said main control means and said read-modified-write control data from said access control means, comprising: second memory plane processing means for receiving said first transfer data from said first data bus as first operation data at a second half of each machine cycle and performing a first operation designated by said memory plane control instruction, on said first operation data to obtain second image data, and second memory plane memory means for storing said second image data at said second address at said second half of each machine cycle.

Claim 3

An apparatus according to claim 1, wherein said second memory plane processing means comprises: table means storing operation results; and referring means for referring to said table means in accordance with said first operation data to obtain said second image data.

Claim 4

An apparatus according to claim 1, wherein said processing command is a copy command.

Claim 5

An apparatus according to claim 1, wherein an identical memory address area is assigned to said first memory plane and second memory plane memory means, said processing command is a copy command associated with an memory address sub-area in said identical memory address area, said access control means includes means for generating and outputting onto said first address bus said first address, said second memory plane further comprises means for outputting said first address over said first address bus as said second address.

Claim 6

An apparatus according to claim 1, further comprising a second data bus, to which said first and second memory planes are connected, and wherein said processing command is a swap command, said first memory plane further comprises first memory plane processing means for receiving second transfer data from said second data bus as second operation data at said second half of each machine cycle and performing a second operation designated by said memory plane control instruction, on said second operation data to obtain said first image data, said first memory plane memory means further comprises means for storing said first image data at said first address at said second half of each machine cycle, said second memory plane memory means further comprises means for outputting said second image data stored at said second address at said first half of each machine cycle, and said second memory plane further comprises second memory plane data output means for outputting said second image data as said second transfer data onto said second data bus at said first half of each machine cycle.

Claim 7

An apparatus according to claim 5, wherein an identical memory address area is assigned to said first memory plane and second memory plane memory means, said swap command being associated with a memory address sub-area in said identical memory address area, said access control means includes means for generating and outputting onto said first address bus said first address, said second memory plane further comprises means for outputting said first address over said first address bus as said second address to said second memory plane memory means.

Claim 8

An apparatus according to claim 1, further comprising: a third address bus; a second data bus, to which said second memory plane is connected; and a third memory plane connected to said third address bus, said control bus, and said second data bus, and operating in synchronism with said machine cycles and in response to said memory plane control instruction from said main control means and said read-modified-write control data from said access control means, comprising: third memory plane memory means for outputting third image data stored at a third at said first half of each machine cycle, and third memory plane data output means for outputting said third image data as second transfer data onto said second data bus, and wherein said processing command is a three term operation command; said access control means further comprises means for selectively generating and outputting onto said third address bus said third address, said second memory plane further comprises second memory plane data output means for said second image data, which is input thereto at said first half of each machine cycle, to said second memory plane processing means at said second half of each machine cycle, said second memory plane processing means further comprises means for receiving said first and second transfer data from said first and second data buses and said second image data from said second memory plane data output means, as second operation data at said second half of each machine cycle and performing a second operation designated by said memory plane control instruction, on said second operation data to obtain said second image data, and said second memory plane memory means further comprises means for outputting said second image data stored at said second address to said second memory plane data output means at said first half of each machine cycle.

Claim 9

An apparatus according to claim 7, wherein an identical memory address area is assigned to said first memory plane and third memory plane memory means, said three term operation command being associated with an identical memory address sub-area in said identical memory address area, and another memory address sub-area in another memory address area assigned to said second memory plane memory means, said access control means includes means for generating and outputting onto said first and second address buses said first and second addresses, said third memory plane further comprises means for outputting said first address over said first address bus as said third address to said second memory plane memory means.

Claim 12

A method according to claim 9, wherein said performing said first operation step including referring to a table in accordance with said first operation data to obtain said second image data, said table storing operation results.

Claim 13

A method according to claim 9, wherein said processing command is a copy command.

Claim 14

A method according to claim 9, wherein said storing of said second image data includes storing said second image data at said first address of said second memory when an identical memory address area is assigned to said first and second memory and said processing command is a copy command associated with a memory address sub-area in said identical memory address area.

Claim 15

A method according to claim 9, further comprising: in said second memory plane, in synchronism with said machine cycles and in response to said memory plane control instruction and said access control data, transferring as second transfer data said second image data stored at said second address of said second memory onto a second data bus, and in said first memory plane, in synchronism with said machine cycles and in response to said memory plane control instruction and said access control data, receiving said second transfer data from said second data bus as second operation data, performing a second operation designated by said memory plane control instruction, on said second operation data to obtain said first image data, and storing said first image data at said first address of said first memory.

Claim 16

A method according to claim 13, wherein said storing of said second image data includes storing said second image data at said first address of said second memory when an identical memory address area is assigned to said first and second memory and said processing command is a copy command associated with a memory address sub-area in said identical memory address area.

Claim 17

A method according to claim 9, further comprising: generating a third address; and in a third memory plane, in synchronism with said machine cycles and in response to said memory plane control instruction and said access control data, transferring third image data stored at said third address of a third memory as second transfer data onto a third data bus, and wherein said performing of said first operation further comprises: reading out said second image data stored at said second address of said second memory, performing said first operation, designated by said memory plane control instruction, on said first and second transfer data and said read-out second image data and storing an operation result as said second image data at said second address of said second memory.

Claim 18

A method according to claim 15, wherein said transferring said third image data includes making said first address to be said third address when an identical memory address area is assigned to said first and third memory and said processing command is a three term operation associated with an identical memory address sub-area in said identical memory address area.

Claim 19

An image data processing apparatus for processing image data in a pipe line fashion, comprising: first and second address buses; first and second control buses; a first data bus; means for providing an input processing command; main control means for generating an access control instruction and a memory plane control instruction in response to said input processing command; access control means connected to said first and second address buses, said first and second control buses, and said first data bus and operating in synchronism with machine cycles and in response to said access control instruction from said main control means, for selectively generating and respectively outputting onto said first and second address buses first and second addresses, and for generating and respectively outputting read and write control data onto said first and second control buses; a first memory plane connected to said first address bus, said first control bus, and said first data bus, and operating in synchronism with said machine cycles and in response to said memory plane control instruction from said main control means and said read control data from said access control means, comprising: first memory plane memory means for outputting first image data stored at said first address over said first address bus at a first machine cycle of said machine cycles, and first memory plane data output means for outputting said first image data as first transfer data onto said first data bus at said first machine cycle; and a second memory plane connected to said second address bus, said second control bus, and said first data bus, and operating in synchronism with said machine cycles and in response to said memory plane control instruction from said main control means and said write control data from said access control means, comprising: second memory plane processing means for receiving said first transfer data from said first data bus as first operation data at a second machine cycle of said machine cycles and performing a first operation designated by said memory plane control instruction, on said first operation data to obtain second image data, and second memory plane memory means for storing said second image data at said second address at said second machine cycle.

Claim 20

An image data processing apparatus for processing image data in a pipe line fashion, comprising: first and second address buses; first and second control buses; a first data bus; means for providing an input processing command; main control means for generating an access control instruction and a memory plane control instruction in response to said input processing command; access control means connected to said first and second address buses, said first and second control buses, and said first data bus and operating in synchronism with machine cycles and in response to said access control instruction from said main control means, for selectively generating and respectively outputting onto said first and second address buses first and second addresses, and for generating and respectively outputting read and write control data onto said first and second control buses; a first memory plane connected to said first address bus, said first control bus, and said first data bus, and operating in synchronism with said machine cycles and in response to said memory plane control instruction from said main control means and said read control data from said access control means, comprising: first memory plane memory means for outputting first image data stored at said first address over said first address bus at a first machine cycle of said machine cycles, and first memory plane data output means for outputting said first image data as first transfer data onto said first data bus at said first machine cycle; and a second memory plane connected to said second address bus, said second control bus, and said first data bus, and operating in synchronism with said machine cycles and in response to said memory plane control instruction from said main control means and said write control data from said access control means, comprising: second memory plane processing means for receiving said first transfer data from said first data bus as first operation data at a second machine cycle of said machine cycles and performing a first operation designated by said memory plane control instruction, on said first operation data to obtain second image data, and second memory plane memory means for storing said second image data at said second address at said second machine cycle.

Claim 21

An apparatus according to claim 17, wherein said second memory plane processing means comprises: table means storing operation results; and referring means for referring to said table means in accordance with said first operation data to obtain said second image data.

Claim 22

An apparatus according to claim 17, further comprising a second data bus, said first memory plane being connected to said second data bus and said second control bus, said second memory plane being connected to said second data bus and said first control bus, and wherein said processing command is a swap command, said first memory plane further comprises first memory plane processing means for receiving second transfer data from said second data bus as second operation data at said second machine cycle and performing a second operation designated by said memory plane control instruction, on said second operation data to obtain said first image data, said first memory plane memory means further comprises means for storing said first image data at said first address at said second machine cycle, said second memory plane memory means further comprises means for outputting said second image data stored at said second address at said first machine cycle, and said second memory plane further comprises second memory plane data output means for outputting said second image data as said second transfer data onto said second data bus at said second machine cycle.

Claim 23

An apparatus according to claim 17, further comprising: a second data bus, to which said second memory plane is connected; and a third memory plane connected to said third address bus, said first control bus, and said second data bus, and operating in synchronism with said machine cycles and in response to said memory plane control instruction from said main control means and said read control data from said access control means, comprising: third memory plane memory means for outputting third image data stored at a third address at a first half of each machine cycle, and third memory plane data output means for outputting said third image data as second transfer data onto said second data bus at said first machine cycle, and wherein said processing command is a three term operation command, said access control means further comprises means for selectively generating and outputting onto said third address bus said third address, said second memory plane further comprises second memory plane data output means for outputting said second image data, which is input thereto at said first machine cycle, to said second memory plane processing means at said second machine cycle, and said second memory plane processing means further comprises means for receiving said first and second transfer data from said first and second data buses and said second image data from said second memory plane data output means, as second operation data at said second machine cycle and performing a second operation designated by said memory plane control instruction, on said second operation data to obtain said second image data.