Multiprocessor system with power-on reset function

Claim 2

A multiprocessor system with power-on reset, comprising: a plurality of printed circuit boards; a plurality of processors respectively provided on said plurality of printed circuit boards, each circuit board having a respective, individual processor thereon; power supply voltage monitor means, connectable to receive a power supply voltage, for detecting the power supply voltage and for producing a corresponding reset signal in response thereto; a first signal line connecting said power supply voltage monitor means and at least two of said printed circuit boards; and a reset signal line provided in parallel with the first signal line and connecting at least two of said printed circuit boards.

Claim 3

A multiprocessor system with power-on reset, comprising: a plurality of printed circuit boards, at least one of said printed circuit boards connectable to receive a system power source voltage; a plurality of processors, at least one processor provided on each of said printed circuit boards; a connector having two parallel lines to connect at least two of said printed circuit boards; and power supply voltage monitor means, provided on one of said printed circuit boards, for resetting said processors by supplying a reset signal to said printed circuit boards through one of said lines of said connector and for returning the reset signal to the one of said printed circuit boards through the other of said lines of said connector.

Claim 4

A multiprocessor system with power-on reset, comprising: a plurality of printed circuit boards, at least one of said printed circuit boards connectable to receive a system power source voltage; a plurality of processors, at least one processor provided on each of said printed circuit boards; a connector having two parallel lines to connect at least two of said printed circuit boards; and power supply voltage monitor means, provided on one of said printed circuit boards, for resetting said processors by supplying a reset signal to said printed circuit boards through one of said lines of said connector and for returning the reset signal to the one of said printed circuit boards through the other of said lines of said connector.

Claim 5

A multiprocessor system with power-on reset according to claim 2, wherein said processors include reset means for being reset by the reset signal, and wherein said power supply voltage monitor means includes means for sending a low level reset signal to the one of said lines of said connector.

Claim 6

A multiprocessor system with power-on reset according to claim 3, wherein the reset signal is a low level reset signal and said processors are reset by the low level reset signal; and wherein said multiprocessor system further comprises: gate means for waveform shaping the reset signal; and delay means for delaying the reset signal.

Claim 7

A multiprocessor system with power-on reset according to claim 4, wherein said delay means comprises a monostable multivibrator.

Claim 8

A multiprocessor system with power-on reset according to claim 4, wherein said delay means includes means for delaying the reset signal by a delay time to synchronously reset all of said processors.

Claim 9

A multiprocessor system with power-on reset, comprising: a plurality of printed circuit boards; a plurality of processors, at least one processor provided on each of said printed circuit boards; a reset signal line connecting at least two of said printed circuit boards; first power supply voltage monitor means, provided on one of said printed circuit boards, for detecting a power supply voltage and for providing a first reset signal responsive to the detecting; and second power supply voltage monitor means, provided on another of said printed circuit boards, for receiving the first reset signal and for providing a second reset signal over said reset signal line to reset said processors, the second reset signal provided responsive to receiving the first reset signal.

Claim 10

A multiprocessor system with power-on reset, comprising: a plurality of printed circuit boards; a plurality of processors, at least one processor provided on each of said printed circuit boards; a reset signal line connecting at least two of said printed circuit boards; first power supply voltage monitor means, provided on one of said printed circuit boards, for detecting a power supply voltage and for providing a first reset signal responsive to the detecting; and second power supply voltage monitor means, provided on another of said printed circuit boards, for receiving the first reset signal and for providing a second reset signal over said reset signal line to reset said processors, the second reset signal provided responsive to receiving the first reset signal.

Claim 11

A multiprocessor system with power-on reset according to claim 7, further comprising a connector having first and second lines operatively connecting said printed circuit boards, and wherein the second reset signal from said second power supply voltage monitor means is supplied to said printed circuit boards through the first line of said connector and the first reset signal is supplied to the at least one processor in the one of said printed circuit boards through the second line of said connector to reset the at least one processor therein.

Claim 12

A multiprocessor system with power-on reset according to claim 8, wherein the one of said printed circuit boards is connected to the other of said printed circuit boards through said connector.

Claim 13

A multiprocessor system with power-on reset according to claim 9, wherein the at least one processor provided on the other of said printed circuit boards is reset by a low level of the second reset signal, and wherein said second power supply voltage monitor means includes means for providing an output to the first line of said connector.

Claim 14

A multiprocessor system with power-on reset according to claim 10, further comprising gate means for gating a signal and delay means for delaying a signal, and wherein said first power supply voltage monitor means and said gate means are operatively connected to the first line of said connector received through said gate means and operatively connected to a second of said printed circuit boards, and wherein said first power supply voltage monitor means is operatively connected to the at least one processor of the second of said printed circuit boards through said delay means and is operatively connected to the at least one processor of the one of said printed circuit boards through the second line of said connector.

Claim 15

A multiprocessor system with power-on reset according to claim 10, wherein said delay means comprises a monostable multivibrator.

Claim 16

A multiprocessor system with power-on reset according to claim 12, wherein said delay means includes means for generating the second reset signal and for delaying the first reset signal by a delay time to synchronously reset said processors.

Claim 17

A multiprocessor system with power-on reset, comprising: a plurality of printed circuit boards; a plurality of processors, at least one processor provided on each of said printed circuit boards; first power supply voltage means, connectable to receive a power supply voltage and provided on one of said printed circuit boards, for providing a reset signal by detecting the power supply voltage; a first signal line connecting said first power supply voltage means to at least one of said processors located on all other of said printed circuit boards; and a second signal line provided in parallel with the first signal line and connecting said processors located on the all other of said printed circuit boards to the at least one processor provided on the one of said printed circuit boards.

Claim 18

A multiprocessor system with power-on reset, comprising: a plurality of printed circuit boards; a plurality of processors, at least one processor provided on each of said printed circuit boards; first power supply voltage means, connectable to receive a power supply voltage and provided on one of said printed circuit boards, for providing a reset signal by detecting the power supply voltage; a first signal line connecting said first power supply voltage means to at least one of said processors located on all other of said printed circuit boards; and a second signal line provided in parallel with the first signal line and connecting said processors located on the all other of said printed circuit boards to the at least one processor provided on the one of said printed circuit boards.

Claim 19

A multiprocessor system according to claim 14, comprising: gate means for waveform shaping the reset signal and for providing a first signal based on the waveform shaping; and delay means for providing a second reset signal responsive to delaying the first signal to reset said processors simultaneously.

Claim 20

A multiprocessor system according to claim 15, wherein said delay means comprises a monostable multivibrator.

Claim 21

A multiprocessor system according to claim 14, further comprising: second power supply voltage means, provided on one of the all other of said printed circuit boards, for providing a second reset signal to reset said processors responsive to receiving the reset signal.

Claim 22

A multiprocessor system with power on reset, comprising: a master printed circuit board, including: master power supply monitoring means for detecting a power supply voltage, for receiving a first reset signal and for providing a second reset signal responsive to receipt of the first reset signal and detection of the power supply voltage, delay means for delaying the second reset signal and for providing a third reset signal responsive to the second reset signal after the delaying, and a master processor operatively connected to said delay means; a slave printed circuit board, including: slave power supply monitoring means for detecting the power supply voltage and for providing the first reset signal responsive to detection of the power supply voltage, a slave processor operatively connected to said delay means, the third reset signal resetting said master processor and said slave processor simultaneously.

Claim 23

A multiprocessor system with power on reset, comprising: a master printed circuit board, including: master power supply monitoring means for detecting a power supply voltage, for receiving a first reset signal and for providing a second reset signal responsive to receipt of the first reset signal and detection of the power supply voltage, delay means for delaying the second reset signal and for providing a third reset signal responsive to the second reset signal after the delaying, and a master processor operatively connected to said delay means; a slave printed circuit board, including: slave power supply monitoring means for detecting the power supply voltage and for providing the first reset signal responsive to detection of the power supply voltage, a slave processor operatively connected to said delay means, the third reset signal resetting said master processor and said slave processor simultaneously.

Claim 24

A multiprocessor system according to claim 18, wherein said slave printed circuit board further includes gate means for waveform shaping the first reset signal.

Claim 25

A multiprocessor system according to claim 18, wherein said master printed circuit board of further includes gate means for waveform shaping the first reset signal.