Patent US5297162A successfully refreshed from Google Patents.
US5297162A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for bit timing synchronization in an adaptive direct sequence CDMA communication system
Assignee: Motorola Solutions Inc
•
Filing: 1993-06-04
•
Granted: 1994-03-22
•
Expires: 2013-06-04
Abstract
Abstract In a CDMA communication system (100) capable of communicating between a receiver (20) and a transmitter (10) direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver bit timing and transmitter timing. Transmitter (10) transmits a training bit sequence (31) followed by a transmitter bit timing sequence (33). The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). Receiver bit timing offset is determined based on the representation of the despreading chip sequence and the transmitter bit timing sequence (33).
Inventors
- 👤 Edward K. B. Lee
- 👤 Jimmy Cadd
- 👤 Tracy L. Fulghum
- 👤 Robert S. Babayi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:11
CPC Classifications
H; H04; H04J; H04J13/00; H04B; H04B1/00; H04B1/69; H04B1/707; H04B1/7097; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/046
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
114 words
In a direct sequence CDMA spread spectrum communication system, wherein spread spectrum communication signals comprising binary bits coded with spreading chip sequences are communicated between a transmitter and a receiver; a bit synchronization method for synchronizing receiver bit timing with transmitter bit timing comprising the steps of: a) transmitting a direct sequence spread spectrum communication signal (DS-SS) including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence; b) despreading the DS-SS communication signal based on said redundant training bit sequence to provide a decoded communication signal; and c) determining receiver bit timing offset based on the transmitter bit timing sequence and the decoded communication signal.
Claim 2
Dependent Claim
114 words
In a direct sequence CDMA spread spectrum communication system, wherein spread spectrum communication signals comprising binary bits coded with spreading chip sequences are communicated between a transmitter and a receiver; a bit synchronization method for synchronizing receiver bit timing with transmitter bit timing comprising the steps of: a) transmitting a direct sequence spread spectrum communication signal (DS-SS) including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence; b) despreading the DS-SS communication signal based on said redundant training bit sequence to provide a decoded communication signal; and c) determining receiver bit timing offset based on the transmitter bit timing sequence and the decoded communication signal.
Claim 3
Dependent Claim
29 words
The method of claim 1, wherein said step of despreading the DS-SS communication signal includes the step of: adaptively determining a representation of despreading chip sequence using an equalizer.
Claim 4
Dependent Claim
45 words
The method of claim 2, wherein the DS-SS communication signal includes consecutive non-alternating bits and the transmitter bit timing sequence comprises alternating bits wherein the state of at least one of two consecutive bits is changed from one bit interval to the succeeding bit interval.
Claim 5
Dependent Claim
30 words
The method of claim 3, wherein said step of determining bit timing offset includes the steps of: integrating the decoded communication signal over a receiver bit interval during alternating bits.
Claim 6
Dependent Claim
58 words
The method of claim 4, wherein said step of determining bit timing offset includes the steps of: producing integration of the decoded communication signal over a receiver bit interval during the consecutive non-alternating bits; and determining sign of the bit timing offset by comparing results of integrations produced during consecutive non-alternating bits with that obtained during alternating bits.
Claim 7
Dependent Claim
95 words
In a direct sequence CDMA receiver system capable of receiving spread spectrum communication signals comprising binary bits coded with a spreading chip sequence from a transmitter; a bit synchronization method for synchronizing receiver bit timing with transmitter bit timing comprising the steps of: a) receiving a redundant training bit sequence; b) despreading the DS-SS communication signal based on said redundant training bit sequence to provide a decoded communication signal; c) receiving a transmitter bit timing sequence; and d) determining receiver bit timing offset based on the transmitter bit timing sequence and the decoded communication signal.
Claim 8
Dependent Claim
95 words
In a direct sequence CDMA receiver system capable of receiving spread spectrum communication signals comprising binary bits coded with a spreading chip sequence from a transmitter; a bit synchronization method for synchronizing receiver bit timing with transmitter bit timing comprising the steps of: a) receiving a redundant training bit sequence; b) despreading the DS-SS communication signal based on said redundant training bit sequence to provide a decoded communication signal; c) receiving a transmitter bit timing sequence; and d) determining receiver bit timing offset based on the transmitter bit timing sequence and the decoded communication signal.
Claim 9
Dependent Claim
29 words
The method of claim 6, wherein said step of despreading the DS-SS communication signal includes the step of: adaptively determining a representation of despreading chip sequence using an equalizer.
Claim 10
Dependent Claim
45 words
The method of claim 7, wherein the decoded communication signal includes consecutive non-alternating bits and the transmitter bit timing sequence includes alternating bits wherein the state of at least one of two consecutive bits is changed from one bit interval to the succeeding bit interval.
Claim 11
Dependent Claim
58 words
The method of claim 8, wherein said step of determining chip timing offset includes the steps of: integrating the decoded communication signal over a first receiver bit interval during the consecutive non-alternating bits to produce a first result; and integrating the decoded communication signal over a second receiver bit interval during alternating bits to produce a second result.
Claim 12
Dependent Claim
40 words
The method of claim 9, wherein said step of determining chip timing offset includes the steps of: determining sign of the bit timing offset by comparing results of integrations produced during consecutive non-alternating bits with that obtained during alternating bits.
Claim 13
Dependent Claim
95 words
A CDMA communication system for communicating direct sequence spread spectrum communication signals comprising: a transmitter for transmitting a direct sequence spread spectrum (DS-SS) communication signal including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence; a receiver for receiving said DS-SS communication signal including: despreading means for despreading the DS-SS communication signal based on said redundant training bit sequence and providing a decoded communication signal; and determination means for determining receiver bit timing offset based on said decoded communication signal and said transmitter bit timing sequence.
Claim 14
Dependent Claim
95 words
A CDMA communication system for communicating direct sequence spread spectrum communication signals comprising: a transmitter for transmitting a direct sequence spread spectrum (DS-SS) communication signal including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence; a receiver for receiving said DS-SS communication signal including: despreading means for despreading the DS-SS communication signal based on said redundant training bit sequence and providing a decoded communication signal; and determination means for determining receiver bit timing offset based on said decoded communication signal and said transmitter bit timing sequence.
Claim 15
Dependent Claim
23 words
The communication system of claim 11, wherein said despreading means comprises an equalizer for adaptively determining a representation of a despreading chip sequence.
Claim 16
Dependent Claim
46 words
The communication system of claim 12, wherein the decoded communication signal includes consecutive non-alternating bits and the transmitter bit timing sequence includes alternating bits wherein the state of at least one of two consecutive bits is changed from one bit interval to the succeeding bit interval.
Claim 17
Dependent Claim
55 words
The communication system of claim 13, wherein said equalizer includes a summer for integrating the decoded communication signal over a first receiver bit interval during the consecutive non-alternating bits to produce a first result and for integrating the decoded communication signal over a second receiver bit interval during alternating bits to produce a second result.
Claim 18
Dependent Claim
29 words
The communication system of claim 13, wherein said determination means includes means for determining sign of the bit timing offset by comparing the first result with the second result.
Claim 19
Dependent Claim
78 words
A direct sequence CDMA receiver, comprising: means for receiving a direct sequence spread spectrum communication signal including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence; a despreading means for despreading the DS-SS communication signal based on said redundant training bit sequence and providing a decoded communication signal; and determination means for determining receiver bit timing offset based on said decoded communication signal and said transmitter bit timing sequence.
Claim 20
Dependent Claim
78 words
A direct sequence CDMA receiver, comprising: means for receiving a direct sequence spread spectrum communication signal including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence; a despreading means for despreading the DS-SS communication signal based on said redundant training bit sequence and providing a decoded communication signal; and determination means for determining receiver bit timing offset based on said decoded communication signal and said transmitter bit timing sequence.
Claim 21
Dependent Claim
24 words
The receiver of claim 16, wherein said wherein said despreading means comprise an equalizer for adaptively determining a representation of a despreading chip sequence.
Claim 22
Dependent Claim
45 words
The receiver of claim 17, wherein the decoded communication signal includes consecutive non-alternating bits and the transmitter bit timing sequence includes alternating bits wherein the state of at least one of two consecutive bits is changed from one bit interval to the succeeding bit interval.
Claim 23
Dependent Claim
54 words
The receiver of claim 18, wherein said equalizer includes a summer for integrating the decoded communication signal, over a first receiver bit interval, during the consecutive non-alternating bits to produce a first result and for integrating the decoded communication signal, over a second receiver bit interval, during alternating bits to produce a second result.
Claim 24
Dependent Claim
28 words
The receiver of claim 19, wherein said determination means includes means for determining sign of the bit timing offset by comparing the first result with the second result.
References Cited (Backward Citations)
USRE32905E
Cited
USRE32905F1
Cited
US4355399A
Cited
US4583090A
Cited
US4617674A
Cited
US4901307A
Cited
US5056109A
Cited
US5109390A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-21 | 1997-09-20 | 1998-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-21 | 2001-09-20 | 2002-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-21 | 2005-09-20 | 2006-03-22 | $7700.00 | Window Closed / Lapsed |