Self adjusting CMOS transmission line driver

Claim 1

A MOSFET integrated circuit on a chip comprising: a plurality of substantially identical off-chip driver circuits, each having a final stage consisting of two NMOS output transistors connected in series and operated by a supply voltage in the ohmic region thereof, each of said driver circuits having an output impedance that can be varied by a control voltage, one of said driver circuits being dedicated as a reference driver and driving a first end of a reference transmission line with characteristic impedance substantially equal to the output impedance of the reference driver, and said reference transmission line having a second end in substantially open circuit; means for applying a clock signal to the reference driver; a comparator circuit for comparing the amplitude of the clock signal at said second end of said reference transmission line with said supply voltage and sampling the comparison result at suitable instants in each clock cycle; means for storing sampled comparison results over the entire clock cycle; means for deriving therefrom said control voltage for varying said driver output impedance, and said control voltage rising when said clock signal amplitude at said second end of the reference transmission line is lower than said supply voltage, and said control voltage declining when said clock signal amplitude is higher than said supply voltage; means for applying said control voltage to said substantially identical off-chip driver circuits, including said dedicated reference driver, wherein a node between said NMOS output transistors connected in series forms the output node, and where said output transistors are turned on alternatively to a controlled level of impedance by separate CMOS inverters having said control voltage as their supply voltage.