US5295260A
Expired / Lapsed
US
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Memory range monitoring apparatus for a multiprocessor computer system
Assignee: Silicon Graphics International Corp
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Filing: 1991-05-31
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Granted: 1994-03-15
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Expires: 2011-05-31
Abstract
Abstract The present invention provides an apparatus for monitoring access by a processor in a computing system to certain defined portions of memory. According to the present invention, the user specifies an address or range of address (the "watchword") in memory to be monitored. Each processor contains hardware which monitors outgoing memory references. If the processor attempts to access the defined portion of memory, the present invention generates a signal which is sent back to the issuing processor to inform it that referenced the watchword in memory. The present invention has several applications. In particular however, the present invention can be used in conjunction with debugging software packages as an aid for debugging user software programs on multiprocessing computer systems. Specifically, the present invention can be used to pinpoint which processor in a multiprocessing computer system accessed the watchword portion of memory. For example, if a processor executed an instruction containing an error, causing improper calculation of a write destination address which resulted in data errors in memory, the present invention can pinpoint precisely which processor in the multiprocessing computer system executed the erroneous instruction, thus pinpointing the erroneous code to within a few instructions. An additional feature of the present invention is that it operates wholly independently and in parallel with the output circuitry of a processor. Thus, no additional levels of logic are introduced into the processor-to-memory path, and as a result the present invention does not adversely impact overall system performance.
Inventors
- 👤 Richard D. Pribnow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/30; G06F11/34; G06F11/3466
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
191 words
A method of isolating faulty program code in a multitasking multiprocessing system comprised of a plurality of processors, comprising the steps of: (a) identifying a memory range of addresses which are being addressed in error; (b) setting a watchword lower address corresponding to a base address of the identified memory range; (c) setting a watchword upper address corresponding to a limit address of the identified memory range; (d) issuing in each of the plurality of processors memory reference addresses to produce a plurality of memory reference addresses; (e) receiving the plurality of memory reference addresses; (f) comparing each memory reference address with the watchword lower address and the watchword upper address; (g) generating an output signal if in the comparing step (f) a memory reference address is greater than or equal to the watchword lower address and the memory reference address is less than the watchword upper address; (h) sending the output signal to the processor which issued the memory reference address and interrupting program execution in the processor which issued the memory reference address; and (i) reviewing program code executed by the interrupted processor to isolate the faulty program code.
Claim 2
Independent Claim
191 words
A method of isolating faulty program code in a multitasking multiprocessing system comprised of a plurality of processors, comprising the steps of: (a) identifying a memory range of addresses which are being addressed in error; (b) setting a watchword lower address corresponding to a base address of the identified memory range; (c) setting a watchword upper address corresponding to a limit address of the identified memory range; (d) issuing in each of the plurality of processors memory reference addresses to produce a plurality of memory reference addresses; (e) receiving the plurality of memory reference addresses; (f) comparing each memory reference address with the watchword lower address and the watchword upper address; (g) generating an output signal if in the comparing step (f) a memory reference address is greater than or equal to the watchword lower address and the memory reference address is less than the watchword upper address; (h) sending the output signal to the processor which issued the memory reference address and interrupting program execution in the processor which issued the memory reference address; and (i) reviewing program code executed by the interrupted processor to isolate the faulty program code.
Claim 3
Dependent Claim
30 words
The method according to claim 1 wherein the receiving step (e), comparing step (f) and generating step (g) are performed in parallel with an issuance of a processor memory reference.
Claim 4
Dependent Claim
23 words
The method according to claim 1 further comprising the step of a user setting the watchword lower address and the watchword upper address.
Claim 5
Dependent Claim
17 words
The method according to claim 1 further comprising the step of a user disabling the output signal.
Claim 6
Dependent Claim
21 words
The method according to claim 1 wherein the output signal is an interrupt which is sent back to the issuing processor.
Claim 7
Dependent Claim
16 words
The method according to claim 5 further comprising the step of a user disabling the interrupt.
Claim 8
Independent Claim
151 words
An apparatus for isolating faulty program code in a multitasking multiprocessing system, comprising: means for determining a watchword range of addresses defined by a watchword lower address and a watchword upper address; a plurality of watchword circuitries, each connected to a different one of the plurality of processors, each watchword circuitry including: first register means for storing the watchword lower address; second register means for storing the watchword upper address; third register means for receiving and for storing a processor memory reference address; comparator means connected to the first, second and third register means, for comparing the processor reference address with the watchword lower address and with the watchword upper address; and interrupt means, connected to the comparator means, for interrupting the associated processor if the processor reference address is greater than or equal to the watchword lower address and the processor reference address is less than the watchword upper address.
Claim 9
Independent Claim
151 words
An apparatus for isolating faulty program code in a multitasking multiprocessing system, comprising: means for determining a watchword range of addresses defined by a watchword lower address and a watchword upper address; a plurality of watchword circuitries, each connected to a different one of the plurality of processors, each watchword circuitry including: first register means for storing the watchword lower address; second register means for storing the watchword upper address; third register means for receiving and for storing a processor memory reference address; comparator means connected to the first, second and third register means, for comparing the processor reference address with the watchword lower address and with the watchword upper address; and interrupt means, connected to the comparator means, for interrupting the associated processor if the processor reference address is greater than or equal to the watchword lower address and the processor reference address is less than the watchword upper address.
Claim 10
Dependent Claim
26 words
The apparatus of claim 7 wherein the third register means, comparator means and generating means are connected in parallel with an output port of the processor.
Claim 11
Dependent Claim
21 words
The apparatus of claim 7 further adapted such that a user sets the watchword lower address and the watchword upper address.
Claim 12
Dependent Claim
13 words
The method of claim 7 further including means for disabling the interrupt means.
Claim 13
Dependent Claim
133 words
A computer program debugging apparatus for a multiprocessing computer system, comprising: a plurality of breakpoint circuit means each connected to a write port of a different one of a plurality of processors, each breakpoint circuit means for comparing a write destination address with a watchword range of memory addresses, such that if the write destination address is within the watchword range of memory addresses, the breakpoint circuit means generates an intermediate interrupt signal; a plurality of enabling circuit means, each connected to a different one of the plurality of the breakpoint circuit means each enabling circuit means for logically combining the intermediate interrupt signal with an interrupt enable signal, such that if the intermediate interrupt signal is set and the interrupt enable signal is set, the enabling circuit means generates an interrupt flag.
Claim 14
Dependent Claim
133 words
A computer program debugging apparatus for a multiprocessing computer system, comprising: a plurality of breakpoint circuit means each connected to a write port of a different one of a plurality of processors, each breakpoint circuit means for comparing a write destination address with a watchword range of memory addresses, such that if the write destination address is within the watchword range of memory addresses, the breakpoint circuit means generates an intermediate interrupt signal; a plurality of enabling circuit means, each connected to a different one of the plurality of the breakpoint circuit means each enabling circuit means for logically combining the intermediate interrupt signal with an interrupt enable signal, such that if the intermediate interrupt signal is set and the interrupt enable signal is set, the enabling circuit means generates an interrupt flag.
Claim 15
Dependent Claim
119 words
The computer program debugging apparatus of claim 11 wherein each breakpoint circuit further includes: first register means for storing a value equal to a base address of the watchword range of memory addresses; second register means for storing a value equal to a limit address of the watchword range of memory addresses; third register means connected to the write port for storing the write destination address; and comparator means, connected to the first, second and third register means, for comparing the values stored in the first, second and third register means and for generating the intermediate interrupt signal when the value stored in the third register means is within the values stored in the first and second register means.
Claim 16
Dependent Claim
64 words
The computer program debugging apparatus of claim 12 wherein the comparator means is further adapted for generating the intermediate interrupt signal if the value stored in the third register means is greater than or equal to the value stored in the first register means and the value stored in the third register means is less than the value stored in the second register means.
Claim 17
Dependent Claim
35 words
The computer program debugging apparatus of claim 11 wherein the enabling circuit means is further adapted for logical AND ing of the intermediate interrupt signal and the interrupt enable signal to generate the interrupt flag.
Claim 18
Dependent Claim
71 words
The computer program debugging apparatus of claim 11 wherein the breakpoint circuit means is connected to the write port in parallel with processor output means for transmitting input/output messages between the processor and a shared memory, such that the breakpoint circuit means and the enabling circuit means do not insert any additional layers of logic between the processor and the shared memory and hence produce no associated degradation in system performance.
Claim 19
Dependent Claim
21 words
The computer program debugging apparatus of claim 11 further adapted such that a user defines the watchword range of memory addresses.
Claim 20
Dependent Claim
15 words
The computer program debugging apparatus of claim 11 further including means for disabling the interrupt.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-14 | 1997-09-13 | 1998-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-14 | 2001-09-13 | 2002-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-14 | 2005-09-13 | 2006-03-15 | $7700.00 | Window Closed / Lapsed |