US4937740A — Real time software analyzing system for storing s…

Claim 1

Independent Claim 205 words

A software analysis system for analyzing a computer program in real time comprising: (a) a probe connected to a microprocessor of a data processing system for receiving first signals to and from said microprocessor representing each address generated by said data processing system during the running of said computer program, said first signals comprising m-bit addresses defining microprocessor memory locations; (b) tag generator means for receiving each said m-bit address from said probe and for generating for each said address an n-bit coded tag wherein m is greater than n, m and n are both position integers; (c) storage controller means coupled to said tag generator means for examining each said coded tag and for generating a second signal indicating whether to store a particular coded tag in memory; (d) first-in, first-out memory means coupled to said tag generator means for receiving said n-bit coded tags therefrom, and responsive to said second signal from said storage controller means for storing certain ones of said coded tags in said memory means at a first variable rate; and (e) data reduction computer means for extracting said coded tags stored in said first-in, first-out memory means in real time at a second variable rate for analysis and display.

Claim 2

Dependent Claim 205 words

A software analysis system for analyzing a computer program in real time comprising: (a) a probe connected to a microprocessor of a data processing system for receiving first signals to and from said microprocessor representing each address generated by said data processing system during the running of said computer program, said first signals comprising m-bit addresses defining microprocessor memory locations; (b) tag generator means for receiving each said m-bit address from said probe and for generating for each said address an n-bit coded tag wherein m is greater than n, m and n are both position integers; (c) storage controller means coupled to said tag generator means for examining each said coded tag and for generating a second signal indicating whether to store a particular coded tag in memory; (d) first-in, first-out memory means coupled to said tag generator means for receiving said n-bit coded tags therefrom, and responsive to said second signal from said storage controller means for storing certain ones of said coded tags in said memory means at a first variable rate; and (e) data reduction computer means for extracting said coded tags stored in said first-in, first-out memory means in real time at a second variable rate for analysis and display.

Claim 3

Dependent Claim 21 words

The software analysis system of claim 1 where a ratio of m to n is greater than or equal to 2.

Claim 4

Dependent Claim 19 words

The software analysis system of claim 2 wherein said tag generator means comprises a set of staggered static RAMs.

Claim 5

Dependent Claim 46 words

The software analysis system of claim 1 further including time stamp counter means coupled to said first-in first-out memory means for marking each one of said digitally coded tags stored in said first-in first-out memory means with a timing code to indicate its time of occurrence.

Claim 6

Dependent Claim 46 words

The software analysis system of claim 4 further including display means couple to said first-in first-out memory means for displaying a frequency of occurrence of each of the stored coded tags and the time elapsed between the occurrence of selected ones of said stored coded tags.

Claim 7

Dependent Claim 63 words

The software analysis system of claim 1 further including qualifier recognition RAM means connected to said probe for examining portions of said computer program first signals which qualify a parameter of said addresses, and for providing a third signal to said storage controller means to indicate whether a particular address is of a type which is to be saved in said memory means.

Claim 8

Dependent Claim 193 words

In a software analyzing system having processing means and memory means, a method of analyzing by said system a computer program containing a set of coded instructions while said program is operating a data processing system which includes a microprocessor, said microprocessor having an address space, comprising the steps of: (a) electronically receiving signals provided to and from said microprocessor while said computer program is being executed by said data processing system; (b) acquiring each one of said signals corresponding to addresses within said address space, said addresses containing m bits, and generating therefrom digitally coded tag signals representing said addresses by combining said m bits of each of said addresses to yield an n-bit tag where m is greater than n, m and n are both positive integers; (c) storing predetermined ones of said digitally coded tag signals in said memory means in real time; (d) marking each one of said digitally coded tag signals stored in said memory means with a timing code to indicate its time of occurrence; and (e) extracting said digitally coded signals from said memory means at a predetermined rate in real time for analysis or display.

Claim 9

Dependent Claim 193 words

In a software analyzing system having processing means and memory means, a method of analyzing by said system a computer program containing a set of coded instructions while said program is operating a data processing system which includes a microprocessor, said microprocessor having an address space, comprising the steps of: (a) electronically receiving signals provided to and from said microprocessor while said computer program is being executed by said data processing system; (b) acquiring each one of said signals corresponding to addresses within said address space, said addresses containing m bits, and generating therefrom digitally coded tag signals representing said addresses by combining said m bits of each of said addresses to yield an n-bit tag where m is greater than n, m and n are both positive integers; (c) storing predetermined ones of said digitally coded tag signals in said memory means in real time; (d) marking each one of said digitally coded tag signals stored in said memory means with a timing code to indicate its time of occurrence; and (e) extracting said digitally coded signals from said memory means at a predetermined rate in real time for analysis or display.

Claim 10

Dependent Claim 33 words

The method of claim 7 further including as step (f): (f) displaying the frequency of occurrence of certain ones of said digitally coded tag signals and a time elapsed between each said occurrence.

Claim 11

Dependent Claim 19 words

The method of claim 7 wherein a ratio of m to n is greater than or equal to 2.

Claim 12

Dependent Claim 193 words

In a software analyzing system having processing means and first-in first-out memory means, a method of analyzing by said system a computer program containing a set of coded instructions while said program is operating a data processing system which includes a microprocessor, said microprocessor having an address space, comprising the steps of: (a) electronically receiving signals provided to and from said microprocessor while said computer program is being executed by said data processing system; (b) acquiring each one of said signals corresponding to addresses within said address space, said addresses containing m bits, and generating therefrom digitally coded tag signals representing said addresses by combining said m bits of each of said addresses to yield an n-bit tag where m is greater than n, m and n are both positive integers; (c) examining each one of said n-bit tag signals to determine whether it should be stored in memory; (d) storing certain ones of said tag signals in said first-in first-out memory means at a first variable clock rate; (e) simultaneously with step (d); extracting said tag signals from said first-in first-out memory means at a second variable rate for analysis or display.

Claim 13

Dependent Claim 193 words

In a software analyzing system having processing means and first-in first-out memory means, a method of analyzing by said system a computer program containing a set of coded instructions while said program is operating a data processing system which includes a microprocessor, said microprocessor having an address space, comprising the steps of: (a) electronically receiving signals provided to and from said microprocessor while said computer program is being executed by said data processing system; (b) acquiring each one of said signals corresponding to addresses within said address space, said addresses containing m bits, and generating therefrom digitally coded tag signals representing said addresses by combining said m bits of each of said addresses to yield an n-bit tag where m is greater than n, m and n are both positive integers; (c) examining each one of said n-bit tag signals to determine whether it should be stored in memory; (d) storing certain ones of said tag signals in said first-in first-out memory means at a first variable clock rate; (e) simultaneously with step (d); extracting said tag signals from said first-in first-out memory means at a second variable rate for analysis or display.

Claim 14

Dependent Claim 47 words

The method of claim 10 further including the step of each examining portions of said acquired signal which qualify a parameter relating to each of said addresses to determine if each said address is of a type which is to be saved in said first-in first-out memory.

Claim 15

Dependent Claim 25 words

The method of claim 10 further including the step of displaying a frequency of occurrence of each tag signal stored in said first-in first-out memory.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1993-06-25	1993-12-25	1994-06-26	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1997-06-25	1997-12-25	1998-06-26	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2001-06-25	2001-12-25	2002-06-26	$7700.00	Window Closed / Lapsed

Real time software analyzing system for storing selective m-bit addresses based upon correspondingly generated n-bit tags

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