US5295259A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data cache and method for handling memory errors during copy-back
Assignee: Advanced Micro Devices Inc
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Filing: 1991-02-05
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Granted: 1994-03-15
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Expires: 2011-02-05
Abstract
Abstract Apparatus and method of a data cache which provides for the handling of errors during data copy-back from a data cache write buffer to external memory in a processing system including a processor. When data requested by the processor at an addressed storage location of the data cache is data which is valid, modified, and other than the data requested by the processor, the data is first transferred to the data cache write buffer and then written back to external memory after the requested data is fetched from a memory bus. If an error occurs during the write back of the data from the write buffer to external memory, the data is transferred from the write buffer to the storage location of the data cache originally addressed by the processor before the memory bus is released.
Inventors
- 👤 Stephen C. Horne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:26
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/073; G06F11/0721; G06F11/0724; G06F11/0793; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
283 words
A data cache for use in a processing system of the type including a processor implemented in an integrated circuit, an external memory for storing data, and a memory bus coupling said processor to said external memory, said data cache being integrated with said processor within said integrated circuit, said data cache comprising: storage means, including a plurality of addressable storage locations, for storing data; a write buffer for temporarily storing data; logic means coupled to said processor and being responsive to a load request generated by said processor, said load request identifying requested data required by said processor, said load request including a storage location address designating one of said plurality of storage locations of said storage means, said designated storage location containing presently stored data, said logic means determining whether said presently stored data is said requested data and causing said presently stored data to be stored in said write buffer as transferred data when said presently stored data is valid and modified, and is not said requested data; read means, responsive to said logic means, for fetching said requested data from said memory bus when said presently stored data is not said requested data, and for storing said requested data in said designated storage location; and load means for conveying said requested data to said processor; said logic means being further arranged to cause said transferred data to be conveyed from said write buffer to said external memory over said memory bus; said logic means being responsive to an error signal indicating unsuccessful conveyance of said transferred data from said write buffer to said external memory to cause said transferred data to be written back into said designated storage location.
Claim 2
Dependent Claim
283 words
A data cache for use in a processing system of the type including a processor implemented in an integrated circuit, an external memory for storing data, and a memory bus coupling said processor to said external memory, said data cache being integrated with said processor within said integrated circuit, said data cache comprising: storage means, including a plurality of addressable storage locations, for storing data; a write buffer for temporarily storing data; logic means coupled to said processor and being responsive to a load request generated by said processor, said load request identifying requested data required by said processor, said load request including a storage location address designating one of said plurality of storage locations of said storage means, said designated storage location containing presently stored data, said logic means determining whether said presently stored data is said requested data and causing said presently stored data to be stored in said write buffer as transferred data when said presently stored data is valid and modified, and is not said requested data; read means, responsive to said logic means, for fetching said requested data from said memory bus when said presently stored data is not said requested data, and for storing said requested data in said designated storage location; and load means for conveying said requested data to said processor; said logic means being further arranged to cause said transferred data to be conveyed from said write buffer to said external memory over said memory bus; said logic means being responsive to an error signal indicating unsuccessful conveyance of said transferred data from said write buffer to said external memory to cause said transferred data to be written back into said designated storage location.
Claim 3
Dependent Claim
56 words
A data cache as defined in claim 1 further including bus control means for acquiring said memory bus to enable the fetching of said requested data and wherein said bus control means is arranged to hold said memory bus until after said transferred data is written back into said designated storage location of said storage means.
Claim 4
Dependent Claim
240 words
In a processing system of the type including a processor implemented in an integrated circuit, an external memory for storing data, a memory bus coupling said processor to said external memory, and a data cache integrated with said processor within said integrated circuit and including storage means, including a plurality of addressable storage locations for storing data, and a write buffer, a method for handling errors during copy-back of data from said cache to said external memory and comprising the steps of: receiving at said data cache a load request identifying requested data, said load request including a storage location address designating one of said plurality of storage locations of said storage means, said designated storage location containing presently stored data; determining whether said presently stored data is said requested data; transferring said presently stored data to said write buffer as transferred data when said presently stored data is valid and modified, and is not said requested data; fetching said requested data from said memory bus when said presently stored data is not said requested data; storing said requested data in said designated storage location; conveying said requested data to said processor; copying-back said transferred data from said write buffer to said external memory over said memory bus; and transferring said transferred data back to said designated storage location upon receipt of an error signal indicating unsuccessful copying-back of said transferred data from said write buffer to said external memory.
Claim 5
Dependent Claim
240 words
In a processing system of the type including a processor implemented in an integrated circuit, an external memory for storing data, a memory bus coupling said processor to said external memory, and a data cache integrated with said processor within said integrated circuit and including storage means, including a plurality of addressable storage locations for storing data, and a write buffer, a method for handling errors during copy-back of data from said cache to said external memory and comprising the steps of: receiving at said data cache a load request identifying requested data, said load request including a storage location address designating one of said plurality of storage locations of said storage means, said designated storage location containing presently stored data; determining whether said presently stored data is said requested data; transferring said presently stored data to said write buffer as transferred data when said presently stored data is valid and modified, and is not said requested data; fetching said requested data from said memory bus when said presently stored data is not said requested data; storing said requested data in said designated storage location; conveying said requested data to said processor; copying-back said transferred data from said write buffer to said external memory over said memory bus; and transferring said transferred data back to said designated storage location upon receipt of an error signal indicating unsuccessful copying-back of said transferred data from said write buffer to said external memory.
Claim 6
Dependent Claim
41 words
A method as defined in claim 3 further including the steps of acquiring said memory bus before the fetching of said requested data and holding said memory bus until after said transferred data is written back into said designated storage location.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-14 | 1997-09-13 | 1998-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-14 | 2001-09-13 | 2002-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-14 | 2005-09-13 | 2006-03-15 | $7700.00 | Window Closed / Lapsed |