Integrated circuit with precharged internal data bus

Claim 2

An integrated circuit, comprising: an array of memory cells; address terminals; means for selecting a memory cell responsive to an address signal received at said address terminals; and a sense amplifier, for sensing the data state of said selected memory cell; a data bus having a data conductor and a dummy data conductor; a data driver, having an input coupled to the output of said sense amplifier for receiving information therefrom, said data driver having a first output for driving said data conductor with a digital value corresponding to said information, and having a second output for driving said dummy data conductor with a complementary digital value, relative to said digital value; a output stage coupled to said data conductor for receiving said digital value from said data conductor; a termination coupled to said dummy data conductor, said termination presenting a load to said dummy data conductor which is substantially similar to the load presented by said output stage to said data conductor; means for generating a control signal; and a transistor having a conduction path connected between said data conductor and said dummy data conductor, and having a control terminal receiving said control signal, for connecting said data conductor and said dummy data conductor together responsive to said control signal.

Claim 3

The circuit of claim 1, wherein said control signal generating means comprises: an address transition detection circuit, coupled to said address terminals, for detecting logic level transitions thereat, one of said logic level transitions indicating that said control signal is to be generated.

Claim 4

An integrated circuit comprising: functional circuitry; a data bus having a data conductor and a dummy data conductor; a data driver, having an input coupled to said functional circuitry for receiving information therefrom, having a first output for driving said data conductor with a digital value corresponding to said information, and having a second output for driving said dummy data conductor with a complementary digital value, relative to said digital value; a output stage coupled to said data conductor for receiving said digital value from said data conductor; and means for generating a control signal; and a transistor having a conduction path connected between said data conductor and said dummy data conductor, and having a control terminal receiving said control signal, for connecting said data conductor and said dummy data conductor together responsive to said control signal; wherein said data bus comprises a plurality of data conductors and a plurality of dummy data conductors, each of said dummy data conductors associated with one of said data conductors; wherein said circuit comprises a plurality of data drivers, each having an input coupled to said functional circuitry for receiving information therefrom, having a first output for driving one of said plurality of data conductors with a digital value corresponding to said information, and having a second output for driving an associated one of said plurality of dummy data conductors with a complementary digital value, relative to said digital value; wherein said circuit comprises a plurality of said output stages, each coupled to one of said plurality of data conductors for receiving said digital value therefrom; and wherein said circuit comprises a plurality of said transistors, each of said plurality of transistors having a conduction path connected between one of said plurality of data conductors and an associated one of said plurality of dummy data conductors, and each having a control terminal receiving said control signal.

Claim 5

An integrated circuit comprising: functional circuitry; a data bus having a data conductor and a dummy data conductor; a data driver, having an input coupled to said functional circuitry for receiving information therefrom, having a first output for driving said data conductor with a digital value corresponding to said information, and having a second output for driving said dummy data conductor with a complementary digital value, relative to said digital value; a output stage coupled to said data conductor for receiving said digital value from said data conductor; and means for generating a control signal; and a transistor having a conduction path connected between said data conductor and said dummy data conductor, and having a control terminal receiving said control signal, for connecting said data conductor and said dummy data conductor together responsive to said control signal; wherein said data bus comprises a plurality of data conductors and a plurality of dummy data conductors, each of said dummy data conductors associated with one of said data conductors; wherein said circuit comprises a plurality of data drivers, each having an input coupled to said functional circuitry for receiving information therefrom, having a first output for driving one of said plurality of data conductors with a digital value corresponding to said information, and having a second output for driving an associated one of said plurality of dummy data conductors with a complementary digital value, relative to said digital value; wherein said circuit comprises a plurality of said output stages, each coupled to one of said plurality of data conductors for receiving said digital value therefrom; and wherein said circuit comprises a plurality of said transistors, each of said plurality of transistors having a conduction path connected between one of said plurality of data conductors and an associated one of said plurality of dummy data conductors, and each having a control terminal receiving said control signal.

Claim 6

An integrated circuit, comprising: functional circuitry; a data bus having a data conductor and a dummy data conductor; a data driver, having an input coupled to said functional circuitry for receiving information therefrom, having a first output for driving said data conductor with a digital value corresponding to said information, and having a second output for driving said dummy data conductor with a complementary digital value, relative to said digital value; a output stage coupled to said data conductor for receiving said digital value from said data conductor; and means for generating a control signal; a transistor having a conduction path connected between said data conductor and said dummy data conductor, and having a control terminal receiving said control signal, for connecting said data conductor and said dummy data conductor together responsive to said control signal; and a parallel data driver, having an input coupled to said functional circuitry for receiving information therefrom, having a first output for driving said data conductor with a digital value corresponding to said information, and having a second output for driving said dummy data conductor with a complementary digital value, relative to said digital value; wherein said data driver and said parallel data driver are controlled by said functional circuitry so as to not simultaneously drive said data conductor with a digital value.

Claim 7

An integrated circuit, comprising: functional circuitry; a data bus having a data conductor and a dummy data conductor; a data driver, having an input coupled to said functional circuitry for receiving information therefrom, having a first output for driving said data conductor with a digital value corresponding to said information, and having a second output for driving said dummy data conductor with a complementary digital value, relative to said digital value; a output stage coupled to said data conductor for receiving said digital value from said data conductor; and means for generating a control signal; a transistor having a conduction path connected between said data conductor and said dummy data conductor, and having a control terminal receiving said control signal, for connecting said data conductor and said dummy data conductor together responsive to said control signal; and a parallel data driver, having an input coupled to said functional circuitry for receiving information therefrom, having a first output for driving said data conductor with a digital value corresponding to said information, and having a second output for driving said dummy data conductor with a complementary digital value, relative to said digital value; wherein said data driver and said parallel data driver are controlled by said functional circuitry so as to not simultaneously drive said data conductor with a digital value.

Claim 8

The circuit of claim 1, further comprising: a first self-biasing circuit coupled to said data conductor, biased by first and second bias voltages, comprising: a pull-up transistor having a conduction path coupled between said data conductor and said first bias voltage, and having a control terminal coupled to said data conductor in such a manner that said pull-up transistor is conductive responsive to said data conductor being at a voltage near said second bias voltage; and a pull-down transistor having a conduction path coupled between said data conductor and said second bias voltage, and having a control terminal coupled to said data conductor in such a manner that said pull-down transistor is conductive responsive to said data conductor being at a voltage near said first bias voltage.

Claim 9

The circuit of claim 5, wherein said first self-biasing circuit further comprises: a first series transistor having a conduction path coupled in series with the conduction path of said pull-up transistor between said data conductor and said first bias voltage; and a second series transistor having a conduction path coupled in series with the conduction path of said pull-down transistor between said data conductor and said second bias voltage; wherein said first and second series transistors each have a control terminal coupled to said control signal generating means in such a manner that said first and second series transistors are conductive responsive to said control signal and non-conductive in the absence of said control signal.

Claim 10

The circuit of claim 5, wherein said output stage comprises: a pull-up transistor having a conduction path coupled between an output node and said first bias voltage, and having a control terminal coupled to said data conductor in such a manner that said pull-up transistor is conductive responsive to said data conductor being at a voltage near said second bias voltage; and a pull-down transistor having a conduction path coupled between said output node and said second bias voltage, and having a control terminal coupled to said data conductor in such a manner that said pull-down transistor is conductive responsive to said data conductor being at a voltage near said first bias voltage.

Claim 11

The circuit of claim 7, wherein said output stage further comprises: a first series transistor having a conduction path coupled in series with the conduction path of said pull-up transistor between said output node and said first bias voltage; and a second series transistor having a conduction path coupled in series with the conduction path of said pull-down transistor between said output node and said second bias voltage; wherein said first and second series transistors each have a control terminal coupled to said control signal generating means in such a manner that said first and second series transistors are non-conductive responsive to said control signal and conductive in the absence of said control signal.

Claim 12

The circuit of claim 8, wherein said first self-biasing circuit further comprises: a first series transistor having a conduction path coupled in series with the conduction path of said pull-up transistor between said data conductor and said first bias voltage; and a second series transistor having a conduction path coupled in series with the conduction path of said pull-down transistor between said data conductor and said second bias voltage; wherein said first and second series transistors each have a control terminal coupled to said control signal generating means in such a manner that said first and second series transistors are conductive responsive to said control signal and non-conductive in the absence of said control signal.

Claim 13

The circuit of claim 5, further comprising: a second self-biasing circuit coupled to said dummy data conductor, biased by said first and second bias voltages, comprising: a pull-up transistor having a conduction path coupled between said dummy data conductor and said first bias voltage, and having a control terminal coupled to said data conductor in such a manner that said pull-up transistor is conductive responsive to said dummy data conductor being at a voltage near said second bias voltage; and a pull-down transistor having a conduction path coupled between said dummy data conductor and said second bias voltage, and having a control terminal coupled to said data conductor in such a manner that said pull-down transistor is conductive responsive to said dummy data conductor being at a voltage near said first bias voltage.

Claim 14

The circuit of claim 5, wherein said output stage comprises: a pull-up transistor having a conduction path coupled between an output node and said first bias voltage, and having a control terminal coupled to said data conductor in such a manner that said pull-up transistor is conductive responsive to said data conductor being at a voltage near said second bias voltage; a pull-down transistor having a conduction path coupled between said output node and said second bias voltage, and having a control terminal coupled to said data conductor in such a manner that said pull-down transistor is conductive responsive to said data conductor being at a voltage near said first bias voltage; a first series transistor having a conduction path coupled in series with the conduction path of said pull-up transistor between said output node and said first bias voltage; and a second series transistor having a conduction path coupled in series with the conduction path of said pull-down transistor between said output node and said second bias voltage; wherein said first and second series transistors each have a control terminal coupled to said control signal generating means in such a manner that said first and second series transistors are non-conductive responsive to said control signal and conductive in the absence of said control signal.

Claim 17

The method of claim 12, wherein said biasing step comprises: responsive to said data conductor having a voltage near said fist voltage, turning on a transistor connected between said data conductor and said second voltage; and responsive to said data conductor having a voltage near said second voltage, turning on a transistor connected between said data conductor and said first voltage.

Claim 20

The method of claim 14, wherein said plurality of memory cells are arranged in a plurality of array blocks; wherein each of said array blocks is associated with one of a plurality of data drivers coupled to said data conductor; and further comprising: selecting one of said array blocks responsive to an address value; and deselecting the data drivers coupled to said data conductor which are associated with unselected array blocks.

Claim 21

The method of claim 14, further comprising: detecting the initiation of an access to a memory cell; wherein said connecting step is performed responsive to said detecting step.